Memory Controller Dynamic Write Distribution Across Unequal Channels

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Solution Overview

Problem

Current memory controllers face inefficiencies in managing data storage operations across multiple channels and memory devices, particularly in balancing workload distribution and optimizing write operations across channels with different numbers of memory devices.

Innovation Solution

A memory controller is designed to monitor memory states and selectively perform write operations across main and reserved memory devices through multiple channels, ensuring efficient use of channels by distributing workload based on memory state information, such as free block counts or valid data sizes, to maintain optimal storage performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a memory controller manages multiple channels with different numbers of memory devices, then storage capacity and flexibility are improved, but workload distribution and channel utilization become unbalanced

Engineering Contradiction:
Improvestorage capacityVSAvoidchannel utilization efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The memory controller dynamically adjusts write operation distribution based on real-time monitoring of free block counts in each channel. Instead of static allocation, the controller adapts the number of write operations to each channel according to current memory state, ensuring optimal utilization even when channels have different numbers of memory devices or varying availability

Inventive Principle:
Principle #15Dynamics

2Productivity

If write operations are distributed across multiple channels, then storage performance is improved, but complexity in managing unequal channel configurations increases

Engineering Contradiction:
Improvestorage performanceVSAvoidworkload management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory controller implements a feedback mechanism where it continuously monitors free block information from each channel and uses this information to determine the number of write operations for each channel. This closed-loop control automatically balances workload distribution without requiring complex manual configuration or intervention

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system enables self-balancing of workload distribution through automatic monitoring and adjustment. The memory controller autonomously determines optimal write operation allocation based on real-time channel status, eliminating the need for external management of unequal configurations

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If reserved memory areas are used to extend storage capacity, then storage flexibility is improved, but management of main and reserved areas becomes more complex

Engineering Contradiction:
Improvestorage flexibilityVSAvoidarea management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory controller merges the management of main memory devices and reserved memory devices into a unified control framework. Both areas are managed through the same channel monitoring and write operation distribution mechanism, simplifying management despite the presence of multiple storage areas with different characteristics

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11543998B2Memory controller for controlling different numbers of memory devices and storage device including the same
Publication Date: 2023.01.03 MIMIRIP LLC
  • US11543998B2 patent drawing
  • US11543998B2 patent drawing
  • US11543998B2 patent drawing

AI summary

A storage device includes first and second memory devices, and a memory controller. The first memory devices correspond to a main data area. The second memory devices correspond to a reserved area. The memory controller is coupled to the first and second memory devices through first and second channels. A number of first memory devices coupled to the memory controller through the first channel is equal to a number of first memory devices coupled to the memory controller through the second channel, and a number of second memory devices coupled to the memory controller through the first channel is different from a number of second memory devices coupled to the memory controller through the second channel. The memory controller selects a memory device on which a write operation is to be performed, based on a memory state of the first and second memory devices.