Memory Controller ECC Caching for Fast Data Verification
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Solution Overview
Problem
Error correction codes (ECCs) increase storage costs and affect memory performance, and memory devices without ECCs lack error detection and correction capabilities, while those with ECCs may not support multiple error detection and correction schemes.
Innovation Solution
Implement error detection and correction using a corresponding code stored in secondary memory and/or a cache, with the memory controller generating and caching error detection codes to reduce latency and enable flexible error correction schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes (ECCs) are stored in memory with data, then error detection and correction capabilities are provided, but storage costs increase and memory performance is affected
Solution Approach 1:
The patent extracts the ECC storage function from the data memory itself and places it in a separate dedicated memory space. The data is stored in one memory device while the corresponding ECC code is stored in a separate memory location, allowing the data memory to operate at full speed without the overhead of embedded ECC storage, thus maintaining high memory performance while still providing error correction capabilities
Solution Approach 2:
The patent introduces a memory controller as an intermediary component that manages the relationship between data reads and ECC code retrieval. The controller fetches the ECC code from the separate memory location and combines it with the data for error detection and correction, enabling the system to achieve both high performance and reliability without the constraints of embedded ECC storage
2Reliability
If error correction codes (ECCs) are stored in memory with data, then error detection and correction capabilities are provided, but storage costs increase
Solution Approach 1:
The patent separates the storage of data and ECC codes into different memory resources. By extracting the ECC storage function from the data memory, the system can use efficient ECC memory structures that require less space per data element, thereby reducing overall storage costs while maintaining error correction capabilities
Solution Approach 2:
The patent uses a copy of the ECC code stored in a separate memory location instead of embedding it within the data structure. This allows the system to retrieve the ECC code efficiently without consuming additional storage capacity within the data memory, thus reducing storage costs while providing comprehensive error correction
3Ease of manufacture
If a single ECC scheme is used in memory, then implementation is simple, but flexibility to support multiple error detection and correction schemes is limited
Solution Approach 1:
The patent implements a universal memory controller architecture that can handle multiple ECC schemes by retrieving different ECC codes from the separate memory location based on the data type or error correction requirements. This allows a single memory system to support various error detection and correction schemes (such as different ECC algorithms or no ECC) without requiring separate hardware implementations for each scheme, thus achieving both simplicity and flexibility
Data Source
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AI summary
A system, including: a code cache; and a memory controller connected to the code cache, and configured to: receive a read command to read requested data from a location in primary memory connected to the memory controller over a first interface; read first data stored in the location from the primary memory; read a code corresponding to the requested data associated with the read command from the code cache, or from secondary memory connected to the memory controller over a second interface different from the first interface; perform error detection and/or correction based on the first data and the code; select second data based on a result of the error detection and/or correction; and output the second data for the requested data.