Memory Controller ECC Error Correction Method
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in correcting errors beyond their defined error correction capacity, particularly in multi-level memory cells, leading to reduced reliability due to factors like charge loss and disturbances, which limit the number of correctable bits and require additional resources or parity data expansion.
Innovation Solution
A memory system with a memory controller and error correcting circuit (ECC) that retrieves and modifies erroneous bits using error information from multiple memory cells coupled to a common word line, allowing correction of errors outside the conventional error correction capacity without increasing parity data size or ECC resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is used to correct errors in multi-level memory cells, then errors within the defined correction capacity can be corrected, but errors beyond the correction capacity cannot be corrected, leading to reduced reliability
Solution Approach 1:
The invention segments the error correction process into multiple stages: first using conventional ECC to correct errors within its capacity, then using a second correction mechanism to handle remaining errors. This segmentation allows the system to correct errors beyond the original ECC capacity without requiring a complete redesign of the ECC resources.
Solution Approach 2:
The invention introduces a new dimension to error correction by utilizing error information from multiple read operations (first read data and second read data) to construct a syndromic value. This dimensional approach allows correction of errors that would otherwise be beyond the conventional ECC capacity, effectively expanding the correction capability without proportionally increasing ECC resource complexity.
2Reliability
If additional ECC resources or parity data expansion is used to correct more errors, then error correction capacity increases, but device complexity and resource requirements increase
Solution Approach 1:
The invention performs multiple reads of the same data from the memory device, creating copies of the data (first read data and second read data). These copies are then used to generate syndromic values and identify erroneous bits. This copying approach enables enhanced error correction without requiring additional parity data or ECC resources, as the same data is read and processed multiple times.
Solution Approach 2:
The invention changes the parameter being used for error detection and correction by constructing a syndromic value based on the difference between two read operations rather than using traditional parity check methods. This parameter change allows the system to identify and correct errors that would otherwise be undetectable or uncorrectable with conventional ECC, thereby increasing the number of correctable bits without expanding parity data size.
3Reliability
If conventional ECC methods are used, then errors within correction capacity can be corrected, but charge loss and disturbances cause errors beyond correction capacity, reducing data integrity
Solution Approach 1:
The invention prepares for potential charge loss and disturbances by performing multiple read operations and comparing the results. By anticipating that errors may occur due to these harmful factors, the system uses the syndromic value constructed from multiple reads to identify and correct erroneous bits before they result in data corruption, thereby maintaining data integrity despite the presence of charge loss and disturbances.
Solution Approach 2:
The invention implements a feedback mechanism where the syndromic value generated from comparing multiple read operations is used to identify erroneous bits, which are then corrected. This feedback loop allows the system to continuously monitor and correct errors caused by charge loss and disturbances, thereby maintaining high data integrity even in the presence of these harmful factors.
Data Source
AI summary
An error correcting method of a memory controller which controls a nonvolatile memory device includes judging whether first read data read from the nonvolatile memory device is correctable; reading second read data from the nonvolatile memory device when the first read data is uncorrectable; and correcting an error of the first read data based on error information of the second read data and error information of the first read data.