Memory Controller ECC Architecture for Multi-Channel Decoding
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Solution Overview
Problem
Existing memory controllers face complexity and increased circuit scale when attempting to achieve high error correction capability for multiple errors while maintaining a simple decoding process for fewer errors, particularly in semiconductor storage devices.
Innovation Solution
A memory controller architecture that includes multiple error correction decoding units, where each channel performs a first error correction decoding process for smaller errors and a second decoding unit handles larger errors, allowing for efficient error detection and correction across multiple channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple error correction decoding units are provided for each channel to achieve high error correction capability, then the error correction capability is improved, but the device complexity and circuit scale increase
Solution Approach 1:
The patent segments the error correction decoding function into two distinct units: a first error correction decoding unit for correcting s symbols and a second error correction decoding unit for correcting t symbols (where s < t). This segmentation allows the system to handle different error scenarios with appropriately sized decoding units, avoiding the need for all channels to use the more complex t-symbol correction unit, thus resolving the contradiction between error correction capability and device complexity
Solution Approach 2:
The patent implements dynamic selection of error correction decoding units based on the actual error conditions detected in each channel. The system adaptively chooses whether to apply the first or second error correction decoding unit, allowing the decoding process complexity to match the actual error correction needs, thereby avoiding unnecessary complexity while maintaining high error correction capability when required
2Reliability
If a high error correction capability is implemented for all channels, then the reliability is improved, but the circuit scale increases
Solution Approach 1:
The patent applies local quality by providing different error correction decoding capabilities to different channels based on their specific needs. Not all channels are equipped with the full-capability second error correction decoding unit; instead, only channels that require correction of t symbols receive this capability, while other channels use the simpler first error correction decoding unit. This localized allocation of resources reduces the overall circuit scale while maintaining high reliability where needed
Solution Approach 2:
The first error correction decoding unit serves as a universal base-level correction mechanism for all channels, handling the majority of error cases with s-symbol correction. The second error correction decoding unit provides enhanced capability only when required. This multi-functional approach allows the system to achieve high error correction capability with fewer total decoding units by having one unit type serve multiple channels for common cases
Data Source
AI summary
According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s<t) symbols on read data, and a second error correction decoding units that perform an error correction decoding process of correcting t symbols on read data from which an error is detected after the error correction decoding process of correcting s symbols.