Memory Controller ECC Encoding for Trusted Execution

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Solution Overview

Problem

Existing security technologies that use ECC storage for in-line security metadata in computer processors face reduced error coverage due to bit stealing from error-correcting code, leading to reliability and performance issues, particularly in trusted execution environments.

Innovation Solution

The solution involves combining ECC bits with security metadata using a fixed encoding pattern via an XOR operation, allowing for efficient encoding and decoding without stealing bits from the ECC, ensuring 100% single-device data correction and eliminating the need for dedicated bits like the trusted domain bit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If security metadata bits are stored in ECC memory to enable trusted execution environments, then security functionality is improved, but error coverage is reduced due to bit stealing from ECC

Engineering Contradiction:
Improvesecurity functionalityVSAvoiderror coverage
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent transitions from storing security metadata directly in the ECC bit space (0-dimensional overlap) to using a separate dedicated space within the cache line (1-dimensional separation). By allocating a specific bit position independent of the ECC code structure, the solution allows security functionality without compromising error correction capability, thus resolving the contradiction between security and reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the cache line into distinct functional regions: data bits, dedicated security metadata bits, and ECC bits. This segmentation ensures that security metadata does not interfere with ECC error correction, allowing both security functionality and full error coverage to coexist without bit stealing from the ECC code.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If dedicated trusted domain bits are added per cacheline, then trusted execution environment support is improved, but device complexity increases

Engineering Contradiction:
Improvetrusted execution environment supportVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the security metadata storage with the existing cache line structure by utilizing a dedicated bit position within the cache line. This integration approach avoids adding separate memory structures or complex hardware modules, thereby supporting trusted execution environments while minimizing increases in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach maintains full error correction capability while ensuring secure metadata access, reducing the negative impact on reliability, availability, and serviceability, and enabling trusted execution environments without compromising error coverage.

Implementation Method 1

combining ECC bits with security metadata using a fixed encoding pattern via an XOR operation

Methodology Applied
Scientific EffectXOR operation:

Data Source

PatentUS20250103428A1Apparatus and method for efficient encoding for trusted execution environments with full error correction
Publication Date: 2025.03.27 INTEL CORP
  • US20250103428A1 patent drawing
  • US20250103428A1 patent drawing
  • US20250103428A1 patent drawing

AI summary

An apparatus and method for efficient encoding for trusted environments including full error correction. One embodiment of a processor comprises: a plurality of cores to execute instructions;a memory controller coupled to the plurality of cores, the memory controller operable in a first error correction mode and a second error correction mode, the memory controller comprising: a decoder to decode first error correction code (ECC) bits encoded in accordance with the first error correction mode to determine a first syndrome and a second syndrome based on data corresponding to the ECC bits; error detection circuitry to determine whether one or both of the first syndrome and the second syndrome indicates an error in the data; and an encoder to generate second ECC bits in accordance with the second error correction mode, the ECC bits to be encoded based on whether one or both of the first syndrome and the second syndrome indicates an error.