Memory Controller Buffering for Faster ECC Memory Initialization
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Solution Overview
Problem
Existing systems face challenges in initializing large system memory capacities efficiently due to the limitations of smart re-power chips in sourcing continuous data for memory initialization, leading to increased initial program load (IPL) times and inefficiencies in command and data bus management.
Innovation Solution
A method and circuit design that utilize a plurality of redrive buffers to store initialization data patterns and error correcting code patterns, allowing the controller to selectively write these patterns to memory addresses without continuous data transfer across a narrow high-speed bus, enabling efficient memory initialization by pre-storing data in redrive buffers and using error correcting codes to manage address parity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred continuously across the high-speed bus during memory initialization, then data availability for writes is improved, but the narrow bus width (32 transfers at 2 Gb/s) cannot source enough data to stream writes continually
Solution Approach 1:
The patent pre-loads all initialization data patterns and their corresponding ECC codes into the redrive chip's data buffers before the initialization process begins. This preliminary action allows the buffers to be fully stocked with data, enabling the memory initialization to proceed without continuous data transfers across the narrow high-speed bus during the write phase.
Solution Approach 2:
The redrive chip's data buffers serve as an intermediary between the controller and the memory DIMMs. The buffers decouple the data sourcing function from the write operation, allowing writes to proceed at full speed using pre-stored data while the narrow high-speed bus only needs to perform initial buffer loading.
2Ease of operation
If the smart re-power chip passes write commands with data through to memory DIMMs, then direct memory writing is achieved, but command and data bus conflicts increase scheduling complexity
Solution Approach 1:
The patent segments the write operation into two distinct phases: (1) loading data patterns and ECC codes into the redrive chip's data buffers, and (2) pushing the pre-buffered data out to the memory DIMMs. This segmentation removes the scheduling dependency between the command bus and memory bus, as the data is already prepared in the buffers during phase 1, allowing phase 2 to proceed independently.
Solution Approach 2:
The data buffers in the reddrive chip act as an intermediary that decouples command issuance from data transfer. The controller can issue write commands without waiting for data to be transferred across the memory bus, as the data is already staged in the redrive buffers.
3Productivity
If multiple data patterns are stored in redrive buffers with corresponding ECC codes, then initialization efficiency is improved, but buffer memory requirements increase
Solution Approach 1:
The patent optimizes the balance between buffer size and initialization speed by determining the minimum number of data patterns that must be pre-loaded to achieve continuous write capability. Rather than buffering all possible memory data, the system buffers a sufficient subset that enables uninterrupted write operations during initialization.
Data Source
AI summary
In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending an first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.