Memory Controller ECC Mapping for Replay-Resistant Data Security
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Solution Overview
Problem
Existing data storage methods, such as AES-XTS and AES-GCM, fail to securely match plaintexts to corresponding ciphertexts, especially in CXL environments, leading to incomplete security protection and vulnerability to replay attacks.
Innovation Solution
A data security method and system that utilizes a memory controller to store verification information, including count values and ECC values, in redundant ECC bits, ensuring secure data storage without extra space, maintaining high bandwidth and throughput, and preventing replay attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AES-XTS algorithm is used for encryption and decryption in storage module, then data security is improved, but the ability to match plaintext to corresponding ciphertext is lost when two same ciphertexts are obtained
Solution Approach 1:
The patent segments the encryption process by introducing a counter that is divided into multiple fields (first counter field, second counter field, third counter field). Each field serves a specific function: the first field stores the original counter value, the second field stores the encrypted counter value, and the third field stores verification information. This segmentation allows the system to maintain both security and plaintext-ciphertext matching capability.
Solution Approach 2:
The patent introduces an intermediary counter mechanism that mediates between the plaintext and ciphertext. The counter value is encrypted using the same encryption algorithm (AES-XTS) but with a different key derivation process involving the storage address. This intermediary encrypted counter value is then combined with the ciphertext through XOR operation, creating a unique matched pair for each encryption operation while maintaining compatibility with the existing AES-XTS algorithm.
2Reliability
If CXL standard security characteristics are applied between host and device, then security protection is improved, but data in memory may remain in plaintext form and other parts of the device are not protected
Solution Approach 1:
The patent implements a universal encryption approach that can be applied throughout the entire storage system, not just between host and device. The encryption method uses the storage address as part of the key derivation process, ensuring that data at any location in the storage module is protected. This multi-functional approach simultaneously protects data in transit and data at rest, and can be applied to any storage location, making the security mechanism versatile and comprehensive.
3Reliability
If verification information is stored in redundant ECC bit, then secure data storage is achieved without extra space, but device complexity increases
Solution Approach 1:
The patent merges the verification information storage with the existing ECC (Error Correction Code) structure. The counter value, encrypted counter value, and verification information are all stored within the same redundant ECC bits that already exist in the storage system for error correction purposes. This merging approach allows the system to achieve secure data storage with verification capabilities without requiring additional storage space, as the verification information coexists with the error correction data in the same structural framework.
Data Source
AI summary
A data security method and data security system configured to applied to a memory controller are provided. The data security method comprises: receiving a data writing request, wherein the data writing request comprises data to be written to a storage module and a storage address of the data; acquiring verification information of the data; and writing the data into the storage address, and writing the verification information into a redundant ECC bit corresponding to the data. The data security method and data security system according to the present disclosure can achieve the secure storage and reading of the data without extra space overhead, while maintaining high bandwidth and throughput.