Memory Controller ECC Recalculation for Multibit Error Recovery
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Solution Overview
Problem
Newer DDR memory channels with reduced ECC bit width on DIMMs offer less error protection, making it challenging for memory controllers to identify and correct multibit errors, as the internal SEC codes on memory chips can only recover single-bit errors and lack sufficient ECC information to pinpoint error sources.
Innovation Solution
The memory controller employs a process involving ECC code generation, internal SEC code reading, and custom scrambling to identify and correct multibit errors by recalculating ECC codes and comparing them with stored SEC codes across memory devices, allowing for data recovery even when internal memory devices cannot correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If reduced ECC bit width is used in newer DDR memory channels, then device complexity is reduced, but reliability deteriorates due to insufficient error protection
Solution Approach 1:
The patent segments the error checking function into two parts: internal SEC codes stored in each memory device for single-bit error correction, and external ECC codes generated and stored by the memory controller for multibit error detection and correction. This segmentation allows each component to use simpler, smaller codes while collectively providing comprehensive error protection.
Solution Approach 2:
The memory controller acts as an intermediary that generates external ECC codes based on data from multiple memory devices, stores these codes externally, and uses them to correct errors that internal SEC codes cannot handle. This intermediary function enables enhanced error protection without requiring increased ECC bit width within the memory devices themselves.
2Manufacturing precision
If internal SEC codes are used in memory devices, then manufacturing precision is simplified, but measurement precision deteriorates because SEC codes cannot identify multibit error sources
Solution Approach 1:
The error correction system is segmented into internal SEC code functionality for simple single-bit error handling and external ECC code functionality for sophisticated multibit error analysis. The external ECC codes, generated by the memory controller, provide the measurement precision needed to identify multibit error sources while the internal SEC codes maintain manufacturing simplicity.
Solution Approach 2:
The memory controller serves as an intermediary that performs sophisticated error analysis using external ECC codes. When internal SEC codes detect an uncorrectable error, the memory controller uses the external ECC codes to precisely identify the error source and perform correction, thereby achieving high measurement precision without complicating the memory device manufacturing.
3Reliability
If more ECC information is stored in memory devices, then reliability improves, but loss of substance increases due to reduced data storage capacity
Solution Approach 1:
The patent segments error correction information into two categories: minimal internal SEC codes stored in each memory device for single-bit error correction, and external ECC codes stored separately by the memory controller for multibit error handling. This segmentation ensures that memory device storage capacity is preserved while comprehensive error protection is maintained through external code storage.
Solution Approach 2:
The memory controller acts as an intermediary that generates, stores, and manages external ECC codes separately from the data in memory devices. This external storage approach provides enhanced error correction capability without consuming data storage capacity within the memory devices themselves, as the ECC codes are maintained in the controller's separate memory resources.
Data Source
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AI summary
An apparatus is described. The apparatus includes a memory controller to receive data from a memory device. The memory controller includes error checking logic circuitry. The error checking logic circuitry is to receive an error checking code from the memory device. The error checking code is generated within the memory device from the data. The error checking logic circuitry includes circuitry to generate a second version of the error checking code from the data that was received from the memory device and compare the received error checking code with the second version of the error checking code to understand if the data that was received from the memory controller is corrupted.