Memory Controller ECC Parity Update for MLC Read Accuracy
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Solution Overview
Problem
Multi-level cell (MLC) non-volatile memory devices, such as flash memory, face challenges in precise data reading due to overlapping threshold voltage distributions caused by characteristic deterioration and program disturbances, leading to increased error rates as the number of bits programmed in each memory cell increases.
Innovation Solution
The implementation of an operating method and controller that uses Error Correction Code (ECC) encoding and decoding operations, including internal and external parity codes, to efficiently update and read data from semiconductor memory devices, with the addition of dummy codes to handle incomplete storage units, thereby improving data accuracy and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is programmed in each memory cell to increase storage capacity, then data storage density is improved, but read accuracy deteriorates due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the data storage and error correction functions into distinct components. It divides the memory system into memory cells for data storage and separate ECC circuits for error detection and correction. The threshold voltage distribution problem is addressed by segmenting the read operation into multiple steps with different reference voltages, allowing precise identification of data states even when distributions overlap.
Solution Approach 2:
The patent changes the parameters of the read operation by applying multiple different reference voltages (Vref1, Vref2, Vref3) during the read process. Instead of using a single reference voltage, the system performs multiple reads with varying reference voltages to accurately determine the threshold voltage of each memory cell, thereby maintaining read accuracy despite overlapping threshold voltage distributions caused by multi-bit programming.
2Productivity
If the number of bits programmed in each memory cell increases to improve integration, then storage density is improved, but reliability deteriorates due to increased error rates
Solution Approach 1:
The patent implements error correction codes (ECC) as a preventive measure before errors can cause data loss. The system adds redundant parity bits to the data before storage, and uses these parity bits during read operations to detect and correct errors. This beforehand cushioning allows the system to maintain high reliability even when storing multi-bit data per cell, compensating for the increased error rates inherent in MLC operations.
Solution Approach 2:
The patent introduces ECC circuits as an intermediary between the memory cells and the data processing system. The ECC encoder adds redundancy to data before it is written to memory cells, and the ECC decoder uses this redundancy to correct errors during retrieval. This intermediary layer protects the integrity of multi-bit data stored in memory cells, maintaining reliability despite the challenges of high-density storage.
3Reliability
If external parity code updating is performed for all internal codewords to ensure data integrity, then reliability is improved, but processing time increases
Solution Approach 1:
The patent applies partial action by updating external parity codes selectively rather than for all internal codewords uniformly. The system identifies which internal codewords require parity updates based on change detection mechanisms, and only performs external parity updates for those specific codewords. This partial approach maintains data integrity while significantly reducing the processing time compared to updating all parity codes regardless of whether changes occurred.
Data Source
AI summary
An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.