Memory Controller ECC Pipelining Across Multiple Memory Interfaces
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Solution Overview
Problem
Existing nonvolatile memory systems face performance bottlenecks due to the high demands of Error Correction Coding (ECC) operations, which can be costly and require expensive hardware to maintain adequate performance throughout the system's life-cycle, especially as error rates increase over time.
Innovation Solution
Implementing two separate ECC blocks operating at relatively low clock speeds, each dedicated to a different memory interface, allowing for parallel processing and sharing clock signals with other memory controller components, while providing a higher frequency clock signal to the host interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single ECC block is used to handle all memory interfaces, then device complexity is reduced, but system performance becomes bottlenecked due to resource-intensive ECC operations
Solution Approach 1:
The patent divides the single ECC block into multiple separate ECC blocks, with each ECC block dedicated to handling ECC operations for a specific memory interface. This segmentation allows parallel processing of ECC operations across multiple interfaces simultaneously, eliminating the performance bottleneck while maintaining manageable complexity through modular design
2Reliability
If high-speed ECC circuits are used to handle memory degradation, then error correction capability is improved, but cost and design difficulty increase significantly
Solution Approach 1:
By segmenting ECC operations into separate blocks that can operate independently at lower clock speeds, the patent avoids the need for expensive high-speed ECC circuits. Each ECC block processes data at manageable speeds, and parallel execution across multiple blocks achieves the required overall throughput without increasing individual circuit speed requirements
Solution Approach 2:
The patent makes clock signals universal by allowing the same clock signal to be shared across multiple ECC blocks and other memory controller components. This multi-functionality approach reduces the need for separate high-speed clock distributions, simplifying design and reducing cost while maintaining reliable error correction capability
3Productivity
If multiple separate ECC blocks operate at lower clock speeds in parallel, then system performance is improved without requiring expensive high-speed circuits, but device complexity increases
Solution Approach 1:
The patent segments ECC functionality into multiple independent blocks that operate in parallel at lower clock speeds. This segmentation enables faster overall data transfer by distributing the ECC processing load across multiple units, achieving high throughput without requiring any single unit to operate at prohibitively high speeds
Solution Approach 2:
The patent reduces the impact of increased device complexity by making the ECC blocks and clock signals universal and interchangeable. Multiple ECC blocks use standardized interfaces and can share common clock signals and control logic, which simplifies the overall design and makes the increased complexity manageable through modular, reusable components
Data Source
AI summary
A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface.