Memory Controller Dynamic ECC Pool Management
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Solution Overview
Problem
The existing data protection techniques for flash memory, which disable pages with high error correction bit counts, lead to a reduction in storage apparatus lifetime due to increased disabled pages, resulting in inefficient data rewriting durability.
Innovation Solution
A memory controller that dynamically adjusts error correction codes based on block deterioration, using a first error correction code for blocks with low error bits and a second code with higher correction ability for deteriorated blocks, while managing blocks in different pools to optimize storage and extend apparatus lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second reference value is set as large as possible to increase data protection capability, then the error correction ability is improved, but the number of sectors capable of being stored in a physical page decreases, causing an increase in the number of times writing is performed to physical pages and decreasing rewriting durability
Solution Approach 1:
The patent applies local quality by differentiating error correction strategies based on block deterioration levels. Blocks are divided into two pools: a first pool for blocks with fewer error bits using first error correction codes, and a second pool for blocks with more error bits using second error correction codes with higher correction capability. This localized differentiation allows optimal error correction for each block condition without uniformly increasing ECC overhead across all blocks, thereby preserving rewriting durability while improving reliability where needed.
Solution Approach 2:
The patent implements dynamics through the dynamic migration of blocks between pools based on their deterioration levels. The memory controller regularly migrates blocks from the first pool to the second pool when error bit counts exceed a threshold, and can migrate blocks back when deterioration improves. This dynamic adjustment allows the system to adapt error correction strength to actual block conditions, optimizing both reliability and rewriting durability over time.
2Reliability
If data is regularly read from all blocks to execute error correction processing to prevent bit errors, then data reliability is improved, but storage apparatus lifetime is reduced due to increased read operations on deteriorated blocks
Solution Approach 1:
The patent applies local quality by implementing selective error correction processing based on block deterioration levels. Instead of uniformly processing all blocks, the system focuses error correction resources on blocks in the second pool that have exceeded the error bit threshold. This localized approach ensures data reliability is maintained for deteriorated blocks while reducing unnecessary read operations on healthy blocks in the first pool, thereby extending overall storage apparatus lifetime.
Data Source
AI summary
A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.