Memory Controller Data Protection via ECC and Verification
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Solution Overview
Problem
Conventional memory controllers fail to protect data from corruption due to electrostatic discharge, clock jitter, and power margin issues, leading to undetected data corruption in external memory devices.
Innovation Solution
A method that converts logical addresses to physical addresses, writes data with error correction and verification information, and verifies written data to ensure integrity, using error correction coding and cyclical redundancy check coding to protect data from corruption during write and read operations, and includes features for read retry and single event upset detection/correction to handle electrostatic discharge, power margin, and clock jitter events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory controllers store data in external memory devices, then data storage capacity is improved, but data integrity deteriorates due to undetected corruption from electrostatic discharge, clock jitter, and power margin issues
Solution Approach 1:
The patent applies preliminary action by calculating and storing error correction codes (ECC) and verification information before writing data to external memory. The memory controller computes parity bits and cyclical redundancy check codes in advance, then stores them alongside the data in the same external memory device. This preliminary preparation enables automatic detection and correction of errors caused by electrostatic discharge, clock jitter, and power margin variations without requiring retransmission or processor intervention.
Solution Approach 2:
The patent implements feedback through verification information that includes indication of the logical address and error correction codes. After writing data, the memory controller reads back the verification information and compares it with the originally written data. This feedback mechanism enables automatic detection of corruption events and triggers correction operations using the stored ECC, ensuring data integrity is restored without external intervention.
2Reliability
If error correction coding is implemented to protect against data corruption, then data integrity is improved, but device complexity increases due to additional error correction information and verification mechanisms
Solution Approach 1:
The patent applies merging by combining multiple error protection functions into a unified system. The memory controller integrates error correction coding (ECC), cyclical redundancy check (CRC), and verification information storage into a single coherent mechanism. Rather than implementing separate independent error detection and correction systems, the patent merges these functions to share computational resources and storage overhead, thereby reducing overall device complexity while maintaining robust data protection.
Solution Approach 2:
The patent implements self-service by enabling the memory system to automatically detect and correct errors without external processor intervention. The verification information stored in memory includes the logical address indication and error correction codes, which the memory controller uses to autonomously identify and repair corrupted data. This self-service capability eliminates the need for complex external error handling mechanisms and reduces the burden on the processor.
3Reliability
If verification information is stored with each data write operation, then data integrity is improved, but write time increases due to additional read-after-write verification operations
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing error correction codes and verification information during the write operation itself. Rather than performing verification after the data is written and potentially failing multiple times, the system prepares the correction capability in advance. This allows the verification process to proceed quickly and efficiently, minimizing the time penalty of additional read-after-write operations.
Solution Approach 2:
The patent implements partial action by reading only the necessary verification information (such as parity bits and CRC) from the memory device during verification, rather than reading the entire data block. This selective verification approach reduces the time required for verification operations while still providing sufficient error detection and correction capability. The system reads only the minimum necessary information to verify data integrity, thereby minimizing the write time penalty.
Data Source
AI summary
A method for protecting data in a memory is disclosed. The method generally includes steps (A) to (D). Step (A) converts a logical address of one of a plurality of logical units to a physical address of a corresponding one of a plurality of physical units. Each physical unit is configured to store (i) data from a corresponding one of the logical units, (ii) respective error correction information and (iii) respective verification information. Step (B) writes a particular one of the physical units to the memory. Step (C) reads a portion of the particular physical unit from the memory. The portion includes the respective verification information. The respective verification information includes an indication of the logical address. Step (D) verifies the writing according to the respective verification information in the portion.