Memory Controller ECC Transfer for Uninterrupted Read Bursts
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Solution Overview
Problem
Conventional error correction systems in memory devices require additional components and incur performance drops due to increased data throughput, as they implement error correction at multiple component levels rather than providing a robust end-to-end solution.
Innovation Solution
Incorporating a memory controller that transmits and processes error correction code (ECC) values end-to-end, allowing ECC operations to occur at various stages, eliminating the need for multiple ECC schemes and enabling uninterrupted data bursts with ECC values appended or transmitted in parallel to data bursts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction codes (ECC) are implemented at component level with dedicated bus lines and integrated circuits, then data integrity is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges error correction functionality into the memory controller by utilizing existing I/O resources. The memory controller performs ECC operations on data bursts using existing bus lines and integrated circuits, eliminating the need for dedicated ECC bus lines and separate ECC integrated circuits. This combining approach maintains data integrity while reducing device complexity.
Solution Approach 2:
The patent makes existing I/O resources multi-functional by using them for both data transmission and error correction operations. The same bus lines and integrated circuits that handle data bursts are also used to perform ECC operations, making these components universal rather than dedicated to single functions. This reduces the overall number of components required.
2Reliability
If error correction circuits are added to perform ECC operations, then data integrity is improved, but productivity decreases due to reduced data throughput
Solution Approach 1:
The patent enables continuous data transmission by performing ECC operations on data bursts without interrupting the data flow. The memory controller processes ECC operations while data continues to be transmitted through the existing I/O resources, maintaining continuous useful action rather than pausing for error correction processing.
Solution Approach 2:
The patent performs error correction operations on incoming data bursts before the data is fully received or processed. By initiating ECC operations preliminarily during data transmission, the system prepares corrected data in advance, avoiding post-processing delays and maintaining data throughput.
3Reliability
If multiple ECC schemes are implemented at different component levels, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent extracts error correction functionality from multiple component levels and consolidates it into a single location - the memory controller. By taking out ECC operations from individual memory devices and host systems and centralizing them in the memory controller, the system reduces the number of ECC schemes from multiple distributed implementations to a single unified approach.
Solution Approach 2:
The patent merges multiple distributed ECC schemes into a single unified ECC operation performed by the memory controller. Instead of having separate ECC implementations at the host, memory device, and intermediate levels, all error correction functionality is combined into one location, simplifying the overall system architecture while maintaining comprehensive error protection.
Data Source
AI summary
A method can include, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.