Memory Controller ECC Rearrangement for Uncorrectable Error Detection

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Solution Overview

Problem

Existing memory storage systems face challenges in accurately detecting uncorrectable error bits in rewritable non-volatile memory due to interference with read signals, leading to incorrect detection results and potential data loss.

Innovation Solution

A data processing method that involves generating an original ECC code for a data stream, converting it into a second ECC code using a rearrangement rule, and writing both codes into the same or different physical programming units within a rewritable non-volatile memory module, allowing for accurate detection of uncorrectable error bits during read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an ECC circuit is configured to generate ECC codes for error detection and correction, then data reliability is improved, but the system cannot accurately detect uncorrectable error bits when read signals are interfered with

Engineering Contradiction:
Improvedata reliabilityVSAvoiderror bit detection accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary transformation process: the original ECC code is converted into a transformed ECC code through a specific transformation rule before being stored alongside the data. During reading, this transformed code acts as an intermediary that enables accurate detection of uncorrectable errors even when read signals are interfered with, without compromising the original error correction capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter representation of the ECC code by transforming it according to a specific rule. This parameter transformation allows the system to detect uncorrectable error bits accurately while maintaining compatibility with the original ECC correction mechanism, resolving the contradiction between reliability and detection precision

Inventive Principle:
Principle #35Parameter changes

2Reliability

If read signal interference occurs causing data shift, then data integrity is compromised, but traditional ECC mechanisms fail to detect the resulting uncorrectable errors

Engineering Contradiction:
Improvedata integrityVSAvoiduncorrectable error detection
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent performs a preliminary transformation of the ECC code before data storage. This advance preparation creates a transformed ECC code that is specifically designed to enable detection of uncorrectable errors that may occur during subsequent read operations, even when read signal interference causes data shift

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The transformed ECC code serves as an intermediary mechanism that bridges the gap between data storage and error detection. It enables the system to accurately detect uncorrectable errors resulting from read signal interference, which traditional ECC mechanisms cannot identify

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9223648B2Memory storage device, memory controller thereof, and method for processing data thereof
Publication Date: 2015.12.29 PHISON ELECTRONICS
  • US9223648B2 patent drawing
  • US9223648B2 patent drawing
  • US9223648B2 patent drawing

AI summary

A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.