Memory Controller ECC Recovery for Silent Multi-Bit Errors
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Solution Overview
Problem
Existing memory systems face high risks of silent errors and reduced error correction capabilities due to the inability of on-die error correction engines to detect and correct multiple-bit errors, leading to unreliable data storage.
Innovation Solution
A memory error correction method that combines system-level error correction by a memory controller with device-level error correction using on-die engines, leveraging reserved registers to track error status and throttle memory access to ensure accurate data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If on-die error correction engine is used for device-level error correction, then error correction speed is improved, but error correction capability deteriorates when multiple-bit errors occur
Solution Approach 1:
The error correction function is segmented into two levels: device-level error correction by the on-die error correction engine for single-bit errors, and system-level error correction by the memory controller for multiple-bit errors. This segmentation allows each level to optimize for its specific error type, maintaining both speed and reliability.
Solution Approach 2:
The memory controller acts as an intermediary that receives error information from the on-die error correction engine and performs additional error correction when the engine fails to correct errors. This intermediary mechanism ensures that both single-bit and multiple-bit errors are properly handled.
2Loss of time
If on-die error correction engine corrects errors immediately, then error correction time is reduced, but silent error risk increases when multiple-bit errors are misidentified as single-bit errors
Solution Approach 1:
The on-die error correction engine provides feedback to the memory controller about correction status. When correction fails or is uncertain, the memory controller performs additional verification and correction, preventing silent errors while minimizing unnecessary re-read operations.
Solution Approach 2:
The on-die error correction engine performs preliminary error correction for single-bit errors before data leaves the memory device. This preliminary action reduces the burden on the memory controller while maintaining data integrity for simple error cases.
3Reliability
If memory controller performs system-level error correction based on ECC devices, then error correction capability is improved, but data recovery complexity increases when errors occur in multiple memory devices
Solution Approach 1:
The system divides memory devices into data devices and error correcting code devices, with dedicated redundancy resources. This segmentation simplifies the error correction process by providing predefined correction paths for different error scenarios, reducing recovery complexity.
Solution Approach 2:
The system uses more error correcting code devices than the minimum required, providing excessive redundancy resources. This allows the memory controller to correct errors in multiple memory devices without requiring complex cross-device error correction algorithms.
Data Source
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AI summary
A memory error correction method, a memory module, a memory controller, and a processor are provided. In the memory error correction method, when error correction on data obtained from the memory module fails, the memory controller determines a memory device in which an error occurs in the memory module, and further performs error correction on the data again based on the memory device in which the error occurs.