Memory Controller Data Reordering for Faster ECC Decoding
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Solution Overview
Problem
Existing memory controllers require longer error correction times and additional buffer space due to the sequential processing of hard and soft decision data for error correction, leading to inefficiencies in ECC decoding.
Innovation Solution
A memory controller that optimizes ECC decoding by rearranging the order of hard and soft decision data processing, allowing simultaneous or sequential input of data to the ECC circuit, and applying data formatting to reduce decoding time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft decision error correction is performed by using both hard decision data and soft decision data after both are received, then error correction accuracy is improved, but error correction time increases and additional buffer space is required
Solution Approach 1:
The patent applies preliminary action by performing hard decision decoding first to obtain initial error correction results, then using soft decision data to correct remaining errors. This staged approach allows the system to achieve high error correction accuracy without waiting for all data to be fully received and processed simultaneously, thereby reducing the overall error correction time while maintaining reliability.
2Reliability
If soft decision error correction is performed by using both hard decision data and soft decision data after both are received, then error correction accuracy is improved, but additional buffer space is required for temporary storage
Solution Approach 1:
The patent extracts and processes hard decision data separately from soft decision data, performing hard decision decoding first to correct errors independently. This extraction approach allows the system to achieve accurate error correction without storing all data in large buffers simultaneously, thereby reducing the quantity of buffer space required while maintaining error correction accuracy.
3Ease of operation
If hard decision data and soft decision data are processed sequentially for error correction, then processing simplicity is maintained, but ECC decoding efficiency decreases
Solution Approach 1:
The patent segments the error correction process into distinct stages: hard decision decoding stage and soft decision decoding stage. Each stage processes specific data types with dedicated algorithms, maintaining processing simplicity within each segment while improving overall ECC decoding efficiency through the coordinated sequence of segments. This segmentation allows parallel processing paths that enhance productivity without sacrificing operational simplicity.
Data Source
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AI summary
A memory controller including: a data formatter receiving first to N-th hard decision data and first to N-th soft decision data, and performing a formatting operation on the first to N-th hard decision data and the first to N-th soft decision data; and an error correction code (ECC) circuit receiving the first to N-th hard decision data and the first to N-th soft decision data from the data formatter and correcting an error on the first page by ECC decoding processing, wherein the data formatter performs the formatting operation such that the first to N-th hard decision data and the first to N-th soft decision data are provided to the ECC circuit in an order different from an order of the first to N-th hard decision data and the first to N-th soft decision data were received from the memory device.