Memory Controller Scrambling and ECC for NAND Read Errors

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Solution Overview

Problem

Nonvolatile memory devices, such as NAND-type flash memory devices, face reliability issues due to cell-to-cell interference and high error rates, particularly in multi-level cell structures, which necessitate the use of error correction codes to ensure data integrity.

Innovation Solution

An error correction apparatus comprising a scrambler, ECC encoder, ECC decoder, and descrambler is implemented to randomize data, perform ECC encoding and decoding, and restore the original bit array sequence, thereby reducing noise effects and correcting errors in read data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-level cell (MLC) techniques are used to increase integration density, then the number of bits stored per cell increases, but cell-to-cell interference occurs and data errors increase

Engineering Contradiction:
Improvenumber of bits per cellVSAvoiddata error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by performing scrambling operations on data before it is written to the memory device. The scrambler randomizes the data patterns in advance, preventing the formation of continuous same-level signals that cause noise effects. This preliminary randomization ensures that even when MLC techniques are used to increase bits per cell, the resulting cell-to-cell interference and data errors are minimized because the data patterns written to adjacent cells are randomized and less likely to cause interference.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If advanced process techniques are used to reduce minimum feature size, then integration density increases, but reliability of the memory device degrades

Engineering Contradiction:
Improveminimum feature sizeVSAvoiddata error rate
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by implementing scrambling operations before data writing. The scrambler randomizes data patterns in advance, converting continuous same-level signals into randomized patterns. This preliminary processing compensates for the reliability degradation caused by advanced process techniques by ensuring that even with reduced minimum feature sizes, the actual data patterns stored are less susceptible to manufacturing variations and interference.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies feedback by using randomness checkers that monitor the scrambled data and generate control signals based on the randomness level. The system continuously checks the randomness of scrambled data and adjusts scrambling operations accordingly. This feedback mechanism ensures that even when advanced process techniques introduce variability, the system can detect and compensate for patterns that might lead to errors, thereby maintaining reliability despite reduced feature sizes.

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If nonvolatile memory devices with narrow read margin are used, then data storage capacity increases, but error rate increases due to difficulty in recognizing data differences

Engineering Contradiction:
Improvedata storage capacityVSAvoidread margin
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by scrambling data before writing to the memory device. This randomization prevents continuous same-level patterns that would be particularly problematic for memory devices with narrow read margins. By ensuring that data patterns are randomized in advance, the system reduces the likelihood of storing patterns that are difficult to distinguish during reading, thereby compensating for the narrow read margin while maintaining high storage capacity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies feedback through randomness checkers that monitor data patterns and generate control signals to adjust scrambling operations. This feedback ensures that data patterns suitable for storage in devices with narrow read margins are selected and randomized appropriately, making it easier to recognize data differences during reading while preserving the high storage capacity enabled by multi-level cell structures.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10691530B2Apparatuses and methods for correcting errors and memory controllers including the apparatuses for correcting errors
Publication Date: 2020.06.23 SK HYNIX INC
  • US10691530B2 patent drawing
  • US10691530B2 patent drawing
  • US10691530B2 patent drawing

AI summary

An error correction apparatus may be provided. The error correction apparatus may be configured to perform a scrambling operation before an error correction code (ECC) operation is performed.