Memory Controller ECC Generation for Small Data Writes

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Solution Overview

Problem

Existing semiconductor devices face inefficiencies in data protection when the number of bits to be written into memory is less than the data width, as they either require read-modify-write operations or generate dummy ECC codes, leading to incomplete data protection and potential data corruption.

Innovation Solution

A semiconductor device with a memory controller that stores write data in a sub-memory, generates ECC codes for merged data when multiple write requests share the same address, and verifies data integrity before writing it to the main memory, thereby omitting unnecessary read-modify-write operations and ensuring data protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read-modify-write is performed to generate ECC for small data, then data protection is achieved, but access efficiency is deteriorated

Engineering Contradiction:
Improvedata protectionVSAvoidaccess efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by accumulating multiple write data in the write buffer before ECC generation. When the accumulated data reaches the ECC generation unit's data width, ECC is generated immediately without requiring read-modify-write operations. This preliminary accumulation of data resolves the contradiction by preparing data in advance for efficient batch processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The write buffer serves as an intermediary between the data writing unit and the ECC generation unit. It temporarily stores multiple write data and facilitates their accumulation to the required data width, enabling efficient ECC generation without read-modify-write operations while maintaining data protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If dummy ECC is generated for small data, then access efficiency is improved, but data protection is compromised

Engineering Contradiction:
Improveaccess efficiencyVSAvoiddata protection
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges multiple write data in the write buffer to reach the ECC generation unit's data width. By combining multiple small data units into a complete data width, real ECC codes can be generated that provide actual data protection, eliminating the need for dummy ECC while maintaining access efficiency.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If multiple write data are accumulated in write buffer, then real ECC generation becomes possible, but device complexity increases

Engineering Contradiction:
Improvedata protectionVSAvoidbuffer management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the data writing process into distinct stages: data accumulation in the write buffer, ECC generation when data width is sufficient, and selective merging of write data. This segmentation manages complexity by creating clear, modular processing steps with defined transition conditions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically determines whether to merge write data based on real-time conditions in the write buffer. When accumulated data reaches the required width, the system transitions to ECC generation mode; otherwise, it continues accumulating. This dynamic adaptation optimizes the balance between data protection and operational simplicity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11221789B2Semiconductor device, memory controller, and memory accessing method
Publication Date: 2022.01.11 RENESAS ELECTRONICS CORP
  • US11221789B2 patent drawing
  • US11221789B2 patent drawing
  • US11221789B2 patent drawing

AI summary

When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.