Memory Controller ECC Scheme Switching for Faster Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in efficiently correcting errors in memory modules, which can lead to data loss and system instability.
Innovation Solution
A memory controller is designed to control a memory module comprising multiple data chips, a first parity chip, and a second parity chip. The memory controller includes a system error correction code (ECC) engine and a processor to manage the ECC engine. The ECC engine features an ECC decoder and a memory to store a parity check matrix, allowing it to select an appropriate ECC decoding scheme based on decoding status flags and correct symbol errors in read codewords.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC decoding schemes are used to correct errors in memory modules, then error correction capability is maintained, but decoding time interval increases
Solution Approach 1:
The patent implements dynamic decoding scheme selection that adapts to the actual error conditions detected in memory chips. The system transitions between different decoding modes (erasure correction decoding when errors are detected, standard ECC decoding when no errors are detected) based on real-time decoding status flags, optimizing both speed and reliability
Solution Approach 2:
The patent changes the decoding parameter (decoding scheme type) based on the detected error condition. When decoding status flags indicate errors in specific memory chips, the system switches to erasure correction decoding which has different computational parameters than standard ECC decoding, thereby reducing decoding time while maintaining correction capability
2Productivity
If erasure correction decoding is performed to reduce decoding time, then decoding speed improves, but coverage of misdetection by on-die ECC engines is reduced
Solution Approach 1:
The patent introduces decoding status flags as an intermediary mechanism that bridges the on-die ECC engines and the system ECC decoder. These flags provide additional error information that complements the on-die ECC detection, enabling the system to identify errors that on-die ECC might miss while still using efficient erasure correction decoding
Solution Approach 2:
The system implements feedback through decoding status flags that return error detection information from memory chips to the controller. This feedback mechanism allows the controller to make informed decisions about which decoding scheme to use, ensuring that erasure correction decoding is applied appropriately when errors are detected while maintaining coverage of misdetections
3Reliability
If multiple decoding schemes are implemented to cover various error cases, then error correction reliability improves, but device complexity increases
Solution Approach 1:
The patent segments the decoding process into distinct schemes (erasure correction decoding and standard ECC decoding) that are selected based on error conditions. Each decoding scheme is independently implemented and optimized for specific error scenarios, allowing the system to maintain high reliability without requiring a single complex universal decoder
Solution Approach 2:
The system dynamically selects between different decoding schemes based on decoding status flags rather than implementing all schemes simultaneously. This dynamic selection reduces the effective complexity at any given moment while maintaining the ability to handle various error cases through appropriate scheme selection
Data Source
AI summary
A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.