Memory Controller ECC Switching for Fatigued Nonvolatile Memory
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Solution Overview
Problem
Existing memory technologies face challenges in effectively correcting errors in miniaturized and multivalued memories, leading to increased circuit scale and reduced data storage capacity, as conventional error correcting codes struggle to maintain performance with memory degradation.
Innovation Solution
A memory controller that dynamically adjusts error correction capability based on the fatigue degree of memory areas, switching to higher-capacity encoding methods when degradation exceeds a threshold and ensuring the total parity does not exceed a predetermined amount, thereby optimizing error correction without increasing circuit scale or reducing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data size of parity is increased to improve error correction capability, then error correction capability is improved, but circuit scale increases and user data storage capacity decreases
Solution Approach 1:
The patent implements dynamic switching between different error correction encoding methods (first encoding method with lower correction capability, second encoding method with higher correction capability) based on the fatigue degree of memory areas. This allows the system to adapt error correction strength to actual memory conditions rather than using a fixed high-capability encoding throughout, thereby avoiding unnecessary circuit complexity while maintaining adequate error correction where needed.
Solution Approach 2:
The patent applies different encoding methods to different memory areas based on their individual fatigue degrees. Memory areas with lower fatigue use a first encoding method, while areas with higher fatigue use a second encoding method. This localized approach ensures that high error correction capability is applied only where necessary, optimizing the balance between reliability and circuit scale.
2Reliability
If the data size of parity is increased to improve error correction capability, then error correction capability is improved, but user data storage capacity decreases
Solution Approach 1:
The system dynamically adjusts the encoding method based on memory fatigue degree, switching between a first encoding method (lower parity overhead) and a second encoding method (higher parity overhead). This dynamic adjustment ensures that user data storage capacity is maximized when memory is healthy, while still providing enhanced error correction when degradation is detected.
Solution Approach 2:
Different encoding schemes are applied to different memory areas according to their fatigue levels. Memory areas in good condition use encoding methods with smaller parity overhead, preserving more user data capacity. Only areas showing signs of fatigue use the more robust but space-consuming encoding methods.
3Reliability
If a stronger error correcting code is used to handle miniaturized and multivalued memory errors, then error correction capability is improved, but circuit scale and memory size increase
Solution Approach 1:
The patent implements a dynamic encoding selection mechanism that switches between a first encoding method and a second encoding method based on detected memory fatigue. This allows the system to use lighter-weight error correction codes when memory is healthy, minimizing the memory overhead required for error correction data, while transitioning to stronger codes only when degradation is detected.
Data Source
AI summary
According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.