Memory Controller ECC Segmentation for Read Performance
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Solution Overview
Problem
Traditional memory integrity approaches suffer from significant performance overheads due to the need to load and verify cryptographic message authentication codes (MAC) and error correction codes (ECC) during every memory access, leading to storage, performance, and bandwidth inefficiencies.
Innovation Solution
The proposed solution involves splitting the ECC into two tiers: Tier I, which stores error detection and MAC data proximate to the data line for every read operation, and Tier II, which stores the full error correction data in a sequestered location, accessed only when an error is detected, thereby reducing unnecessary data retrieval during normal read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory integrity approaches are used with MAC and ECC loaded on each access, then memory integrity and error correction are ensured, but performance overhead, storage overhead, and bandwidth overhead increase significantly
Solution Approach 1:
The patent segments the ECC code into two parts: error detection code stored with data and error correction code stored separately. This segmentation allows the system to perform error detection without always requiring full ECC, reducing the overhead during normal read operations while maintaining correction capability when needed.
Solution Approach 2:
The patent extracts the error correction code from the data line and stores it in a separate location (ECC memory). This extraction allows the system to read only the essential data and error detection information during normal operations, avoiding the performance penalty of loading complete ECC data while preserving the ability to correct errors when detected.
2Reliability
If MAC and ECC are loaded and verified on each memory access, then data integrity is verified, but storage overhead and bandwidth overhead increase
Solution Approach 1:
The patent segments the integrity verification requirements into two components: MAC for data integrity verification (stored with data) and ECC for error detection and correction (stored separately). This segmentation allows the system to verify integrity efficiently without always requiring the full ECC data, reducing storage overhead.
Solution Approach 2:
The patent extracts the error correction code from the data line and stores it in a separate location (ECC memory). This extraction allows the system to read only the essential data and error detection information during normal operations, avoiding the storage overhead of keeping complete ECC data with every data line.
3Reliability
If full ECC data is read during every read operation, then error correction capability is maintained, but bandwidth overhead and performance penalties occur
Solution Approach 1:
The patent segments the ECC data into error detection code (read with data) and error correction code (read separately from ECC memory). This segmentation enables the system to maintain error correction capability while avoiding the bandwidth overhead of reading complete ECC data during every operation, only reading correction data when errors are detected.
Solution Approach 2:
The patent extracts the error correction code from the data line and stores it in a separate location (ECC memory). This extraction allows the system to read only the essential data and error detection information during normal operations, avoiding the bandwidth overhead of loading complete ECC data while preserving the ability to correct errors when detected.
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
A write request causes controller circuitry to write an encrypted data line and Tier I metadata including MAC data and a first portion of ECC data (error detection) to Tier I memory circuitry and a second portion of ECC data (error correction) to sequestered Tier II memory circuitry. A read request causes the controller circuitry to read the encrypted data line and the Tier I metadata from the Tier I memory circuitry. Using the first portion of the ECC data included in the Tier I metadata the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data. If an error in the data line is detected by the controller circuitry, the second portion of the ECC data is fetched from the Tier II memory circuitry and the error corrected.