Memory Controller ECC Transfer Without Dedicated Parity Lines
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Solution Overview
Problem
Conventional error checking and correction (ECC) methods in memory devices require dedicated parity chips and additional data lines, which are costly and inflexible, and cannot be easily upgraded to handle increasing error rates, especially in systems where soft errors occur due to environmental factors.
Innovation Solution
A memory system and method that stores and transfers parity information without a dedicated parity chip or parity data lines by using a memory controller to calculate and embed checksums within burst transactions on the same data lines as data, allowing for flexible implementation of ECC without additional hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated parity chips and additional data lines are used for error checking and correction, then error detection and correction capability is improved, but device complexity and pin-count increase
Solution Approach 1:
The patent merges the parity information storage function with the existing data memory structure by utilizing spare rows or columns in the memory array to store parity bits for ECC codes. This eliminates the need for separate dedicated parity chips and integrates the error correction functionality into the existing memory device architecture, thereby reducing device complexity while maintaining reliability.
Solution Approach 2:
The patent makes the existing memory array serve multiple functions: storing user data and simultaneously storing parity information for error correction. The same memory cells and data lines are used for both data storage and parity storage, eliminating the need for dedicated parity data lines and reducing pin-count while maintaining ECC capability.
2Reliability
If dedicated parity chips and additional data lines are used for error checking and correction, then error detection and correction capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the parity storage function with the existing data memory structure, eliminating the need for separate dedicated parity chips. This integration reduces the total component count and assembly complexity, thereby lowering manufacturing costs while maintaining error detection and correction capability.
Solution Approach 2:
The patent enables the existing memory array to serve dual purposes: storing user data and storing parity information. This multi-functionality eliminates the need for additional dedicated hardware components, reducing bill of materials costs and simplifying the manufacturing process.
3Reliability
If conventional ECC methods are used with fixed hardware configuration, then error checking is provided, but adaptability to changing error rates is reduced
Solution Approach 1:
The patent implements dynamic ECC capability by allowing the memory controller to programmatically configure the parity storage location and adjust the level of error protection based on observed error rates. The system can dynamically select between different ECC modes and adjust parity storage allocation, providing adaptability to changing environmental conditions and error rates while maintaining reliable error checking.
Data Source
AI summary
A memory system and method for generating and transferring parity information within burst transactions of burst read and write transfers and without dedicated parity chips or parity data lines.