Memory Controller ECC Transformation for Multi-Master Cache Safety
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Solution Overview
Problem
Existing memory systems face challenges in maintaining adequate functional safety and managing error correction codes (ECC) across heterogeneous interfaces and memory levels, particularly in multi-level cache systems, due to varying error detection and correction requirements among different masters and memories.
Innovation Solution
A memory controller is configured to calculate and transform ECC syndromes, detect and correct errors, and manage ECC operations across multiple memories and controlling components, ensuring consistent ECC protection and scrubbing transactions to maintain functional safety.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-level cache system with heterogeneous memory controllers is used, then memory capacity and access speed are improved, but error detection and correction management becomes complex due to varying ECC requirements among different masters and memories
Solution Approach 1:
The patent introduces an intermediary ECC management mechanism within the memory controller that automatically transforms ECC syndromes between different types (e.g., SECDED to SEO). This intermediary layer handles the complexity of heterogeneous ECC requirements, allowing different memory masters with varying ECC capabilities to access unified memory resources without each master needing to implement all ECC types, thus resolving the contradiction between improved memory performance and ECC management complexity
Solution Approach 2:
The memory controller is designed with universal ECC management capability that can handle multiple ECC types (SECDED, SEO, and other custom ECC schemes) through a single unified interface. The controller can calculate, transform, and manage different ECC syndromes using the same hardware resources, enabling one memory controller to serve multiple masters with different ECC requirements without requiring separate dedicated ECC management circuits for each master, thereby reducing overall system complexity while maintaining productivity
2Reliability
If ECC syndrome transformation is implemented across heterogeneous interfaces, then functional safety and error correction are improved, but processing time and performance penalty increase
Solution Approach 1:
The patent implements preliminary action by pre-calculating and storing transformation matrices or lookup tables for ECC syndrome conversion between different ECC types. When a memory access occurs, the controller can quickly transform ECC syndromes using these pre-computed values rather than performing complex real-time calculations, significantly reducing the processing time penalty while maintaining reliable error correction and functional safety across heterogeneous interfaces
Solution Approach 2:
The patent replaces complex mechanical or software-based ECC transformation processes with optimized hardware circuitry that performs syndrome transformation in parallel. The hardware implementation uses logical operations and pre-computed transformation constants to convert ECC syndromes between types (e.g., from SECDED to SEO) much faster than sequential software processing, thereby improving reliability through comprehensive error correction while minimizing the loss of processing time
3Adaptability or versatility
If multiple ECC types are supported for different masters, then adaptability and error protection are improved, but device complexity and implementation difficulty increase
Solution Approach 1:
The patent applies local quality by allowing different portions of the memory system to have different ECC characteristics tailored to specific masters' requirements. The memory controller can selectively apply different ECC types (SECDED for safety-critical masters, SEO for performance-critical masters) to different memory regions or transactions based on the master's capabilities and requirements. This localized approach enables high adaptability and error protection where needed while simplifying implementation for other regions, reducing overall manufacturing complexity compared to implementing all ECC types uniformly across the entire system
Data Source
AI summary
A system includes a memory controller, multiple memories coupled to the memory controller, and multiple controlling components coupled to the memory controller. The memory controller calculates an error correction code (ECC) syndrome of a first type for a segment of data; stores the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories; receives a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component implementing an ECC syndrome of a second type; transforms the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type; detects a number of errors, if any, present in the segment of data; and takes further action depending on how many errors are detected.