Memory Controller Endurance Determination Circuit Wear-Leveling
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Solution Overview
Problem
Resistive memory devices experience degradation in endurance due to increased writing and reading cycles, leading to potential data loss and reliability issues, necessitating a method to determine and mitigate this degradation.
Innovation Solution
A memory controller with an error correction code (ECC) circuit and an endurance determination circuit that counts writing operations and error cells to assess endurance degradation, performing re-writing with a lower current and wear-leveling processes to maintain data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If writing and reading cycles increase to improve memory device usage, then productivity is improved, but endurance degrades leading to data loss and reliability issues
Solution Approach 1:
The patent performs preliminary actions by counting writing operations and error cells before endurance degradation becomes critical. The endurance determination circuit proactively monitors write counts and error patterns, enabling early detection of degradation trends and triggering preventive wear-leveling operations before data loss occurs.
Solution Approach 2:
The patent implements feedback mechanisms where the endurance determination circuit continuously monitors writing operation counts and error cell counts, compares them against thresholds, and triggers wear-leveling operations when degradation is detected. This closed-loop feedback system dynamically adjusts memory management based on real-time endurance status.
2Productivity
If the number of writing operations increases to improve data storage capacity utilization, then productivity is improved, but the number of error cells increases causing reliability degradation
Solution Approach 1:
The patent performs preliminary counting of error cells alongside writing operations to identify degradation trends before they lead to data loss. By proactively tracking error cell counts and comparing them against thresholds, the system can trigger wear-leveling operations in advance.
Solution Approach 2:
The endurance determination circuit implements feedback by continuously monitoring error cell counts and writing operation counts, and triggering wear-leveling operations when error rates exceed acceptable thresholds, thereby maintaining reliability despite high utilization.
3Device complexity
If conventional memory controllers are used without endurance determination circuits, then device complexity is reduced, but the ability to detect and measure endurance degradation is insufficient
Solution Approach 1:
The endurance determination circuit performs self-service by autonomously counting writing operations and error cells, comparing counts against stored thresholds, and triggering wear-leveling operations without external intervention. The circuit serves its own monitoring and determination functions, reducing the need for complex external control mechanisms.
Solution Approach 2:
The endurance determination circuit integrates multiple functions into a single component: counting writing operations, counting error cells, comparing counts against thresholds, and triggering wear-leveling operations. This multi-functional approach adds detection capability without proportionally increasing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively determines endurance degradation and prevents data loss by re-writing data with a lower current and performing wear-leveling, ensuring the reliability and longevity of resistive memory devices.
Implementation Method 1
an error correction code (ECC) circuit configured to detect an error from data read from the memory device
Implementation Method 2
an endurance determination circuit configured to check a first counting value indicating a number of writing operations on the memory device and a second counting value indicating, based on the data read from the memory device, at least one of: a number of first memory cells of the memory device, each of the first memory cells having an error, and a number of second memory cells of the memory device in a certain logic state
Implementation Method 3
re-writing data in the first page by using a writing current of a level that is lower than a level of a normal writing current
Data Source
AI summary
Provided are a memory controller determining degradation in endurance, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes: an error correction code (ECC) circuit configured to detect an error from data read from a memory device; and an endurance determination circuit configured to check a first counting value indicating a number of writing operations on the memory device and a second counting value indicating, based on the data read from the memory device, at least one of: a number of first memory cells of the memory device, each of the first memory cells having an error and a number of second memory cells of the memory device in a certain logic state, and configured to perform a first determination operation for determining whether endurance of the memory device has degraded based on a checking result.