Memory Controller Erase Block Assignment Interval

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Solution Overview

Problem

Nonvolatile memory devices face performance degradation due to the time-consuming erase-before-write operation, which can lead to decreased operation efficiency and increased error rates over time.

Innovation Solution

A method is introduced to calculate and adjust the assignment interval for erase blocks in a nonvolatile memory system, allowing for the dynamic management of erase blocks and re-erasing them based on timestamps to ensure timely reassignment, thereby improving system speed and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If erase operations are performed before write operations in nonvolatile memory, then data integrity is maintained, but operation speed decreases due to the time-consuming erase process

Engineering Contradiction:
Improvedata integrityVSAvoidoperation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system performs erase operations in advance during idle periods or background processes, so that when a write operation is requested, the erase operation has already been completed. This preliminary action ensures data integrity is maintained while avoiding delays in write operations, as the erase is already done before the write is needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory controller dynamically adjusts the timing and prioritization of erase operations based on system conditions, write request patterns, and memory block states. By making the erase operation timing flexible rather than fixed, the system can optimize between maintaining data integrity and preserving operation speed under different workload conditions.

Inventive Principle:
Principle #15Dynamics

2Speed

If erase blocks are held in a ready state for extended periods, then write operations can be performed quickly, but errors increase due to prolonged erase block states

Engineering Contradiction:
Improvewrite operation speedVSAvoiderror rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system implements periodic re-erasing of erase blocks that have been in the ready state for extended periods. By periodically refreshing the erase blocks, the system prevents errors that accumulate during prolonged idle states while still maintaining them in a ready state for quick write operations. This periodic maintenance balances speed and reliability.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The memory controller monitors the state and age of erase blocks, and based on this feedback, determines when re-erasing is necessary. The controller tracks how long erase blocks have been in the ready state and uses this information to schedule re-erasing operations before errors occur, thereby maintaining both quick write capability and low error rates.

Inventive Principle:
Principle #23Feedback

3Productivity

If the number of erase blocks is increased to improve write availability, then write operations can proceed faster, but memory management complexity increases

Engineering Contradiction:
Improvewrite availabilityVSAvoidmemory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory controller automatically manages the pool of erase blocks, including tracking their states, determining when re-erasing is needed, and selecting appropriate blocks for write operations. This self-service approach allows the system to maintain a larger pool of ready erase blocks to improve write availability without proportionally increasing management complexity, as the controller handles the complexity automatically.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9870160B2Method of operating memory system including nonvolatile memory and memory controller
Publication Date: 2018.01.16 SAMSUNG ELECTRONICS CO LTD
  • US9870160B2 patent drawing
  • US9870160B2 patent drawing
  • US9870160B2 patent drawing

AI summary

A method of operating a nonvolatile memory (NVM) is provided which includes calculating an assignment interval between successive assignments of erase blocks to free blocks from among a plurality of memory blocks of the NVM, and adjusting a number of erase blocks of the plurality of memory blocks according to the assignment interval. The erase blocks are memory blocks, having an erased state, from among the plurality of memory blocks, and the free blocks are memory blocks, which are selected to write data, from among the erase blocks.