Memory Controller Erase Prohibition for Storage Reliability
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Solution Overview
Problem
The reliability of semiconductor storage devices is compromised due to the reduced scale and altered structure resulting from high integration, leading to potential data damage and degradation of storage device reliability.
Innovation Solution
An operation method for a storage device that includes a nonvolatile memory and a memory controller, which prohibits the erase of memory cells for a critical time by setting some cells to store valid data, managing tables to indicate valid data storage, and releasing these settings after the critical time has elapsed, thereby improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are frequently erased to maintain storage capacity, then storage device productivity is improved, but memory cell reliability deteriorates due to premature erasure before data stabilization
Solution Approach 1:
The patent applies preliminary action by establishing a prohibition period immediately after erasing memory cells. During this critical time window, the memory controller prevents any subsequent erase operations on the same cells, allowing the erased state to stabilize before being eligible for reuse. This proactive timing mechanism ensures data integrity while maintaining storage throughput.
2Reliability
If the prohibition period is extended to ensure data stability, then memory cell reliability is improved, but storage device productivity deteriorates due to reduced erase cycle frequency
Solution Approach 1:
The patent implements dynamics by making the prohibition period adaptive rather than fixed. The memory controller dynamically adjusts the duration of the prohibition period based on factors such as memory cell type, erase conditions, and observed stability patterns. This dynamic adjustment optimizes the balance between ensuring data stability and maintaining high erase cycle frequency for storage productivity.
3Ease of manufacture
If high integration is implemented to reduce production cost, then manufacturing cost is reduced, but memory cell structure complexity increases leading to reliability degradation
Solution Approach 1:
The patent applies feedback by implementing a monitoring and control mechanism that tracks the state and performance of highly integrated memory cells. The memory controller receives feedback about cell status and adjusts the prohibition period and erase scheduling accordingly, compensating for the reduced inherent stability of highly integrated structures while maintaining cost-effectiveness.
Data Source
AI summary
An operation method a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory is provided. The operation method includes erasing memory cells of the nonvolatile memory using the memory controller and prohibiting an erase of the erased memory cells for a critical time using the memory controller.