Nonvolatile Memory Controller Erase Voltage Automation

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Solution Overview

Problem

Conventional nonvolatile memory devices require the test device to directly set the start level of an erase voltage and transmit multiple commands for each sample memory block, increasing the load on the test device during erase operations.

Innovation Solution

A nonvolatile memory device with a controller that autonomously sets the start level of the erase voltage based on test results, using an incremental step pulse erase method and reducing the number of commands needed from the test device by generating and storing test results based on pass erase loop counts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the test device directly sets the start level of erase voltage and transmits multiple commands for each sample memory block, then the erase operation can be performed, but the load on the test device increases

Engineering Contradiction:

Improveerase operation efficiencyVSAvoidtest device load

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The memory device autonomously determines the start level of erase voltage by performing an erase operation with an initial erase voltage, detecting whether the erase is successful, and automatically adjusting the voltage level without requiring external test device intervention. This self-service mechanism transfers the control complexity from the test device to the memory device itself.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The memory device performs a preliminary erase operation with an initial erase voltage before the actual erase operation. Based on the result of this preliminary operation, it determines the appropriate start level for the subsequent erase operation. This preliminary action allows the system to optimize erase parameters in advance, reducing the need for multiple commands during the actual erase process.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If multiple commands are transmitted for each sample memory block, then the erase operation can be controlled, but the number of commands increases the test process complexity

Engineering Contradiction:

Improveerase operation controlVSAvoidtest process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple erase operations into a single streamlined process. Instead of transmitting separate commands for each sample memory block, the memory device performs erase operations autonomously and aggregates results, reducing the number of commands that need to be transmitted between the test device and memory device.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory device acts as an intermediary that manages the erase operation internally. It receives a single command from the test device, then autonomously performs the necessary voltage adjustments and erase operations, and finally returns a consolidated result. This intermediary role simplifies the interaction between the test device and memory device.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of operation

If the test device sets the start level of erase voltage, then the erase operation can be initiated, but the test device must have complex control logic

Engineering Contradiction:

Improveerase operation initiationVSAvoidtest device control logic

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

Instead of having the test device determine and set the start level of erase voltage, the patent inverts the control logic by having the memory device autonomously determine its own erase voltage level. The test device simply provides an initial voltage value, and the memory device independently decides whether to adjust it based on erase success detection, thereby simplifying the test device's control logic.

Inventive Principle:

Principle #13The other way round (Inversion)

4Productivity

If the erase voltage level is adjusted based on pass erase loop count, then the erase operation efficiency is improved, but the memory device must autonomously determine voltage levels

Engineering Contradiction:

Improveerase operation efficiencyVSAvoidvoltage level automation

Core Design Contradiction:

ProductivityVSExtent of automation

Solution Approach 1:

The memory device implements a feedback mechanism where it detects whether the erase operation is successful after applying an erase voltage. Based on this feedback, it automatically determines whether to adjust the erase voltage level and how many loops to repeat the operation. This feedback-driven automation optimizes erase efficiency while maintaining controlled voltage adjustments.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9786374B2Nonvolatile memory device, operating method thereof, and test system for optimizing erase loop operations

Publication Date: 2017.10.10 SK HYNIX INC

AI summary

A nonvolatile memory device includes a plurality of memory blocks. The nonvolatile memory device includes a controller configured to perform an erase operation by repeating an erase loop, and generates and stores a test result based on a pass erase loop count of the erase operation in response to a result processing command. The erase loop includes applying an erase voltage to a target memory block among the memory blocks in response to an erase command.