Memory Controller Erase Voltage Pulse Time Adjustment
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Solution Overview
Problem
Existing memory systems face challenges in optimizing the erase operation of memory cells, leading to potential damage and read errors due to inadequate control over the erase voltage pulse time and initial voltage values, which affects the degree of erasure and storage reliability.
Innovation Solution
A memory system that includes a semiconductor memory device and a controller, where the controller adjusts the pulse time and initial voltage value of the erase voltage based on the erase result, using management tables to determine the optimal voltage settings for each memory cell block, thereby preventing excessive or insufficient erasure states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase voltage pulse time is extended to ensure complete erasure, then the erasure completeness is improved, but the memory cell damage increases
Solution Approach 1:
The patent applies dynamics by making the erase voltage pulse time adjustable rather than fixed. The controller dynamically determines the pulse time based on the memory cell block's erase count, using longer pulse times for blocks with fewer erase counts and shorter pulse times for blocks with higher erase counts, thereby optimizing the balance between erasure completeness and cell damage prevention
Solution Approach 2:
The patent changes the parameter of erase voltage pulse time based on the erase count of memory cell blocks. By storing different pulse time values in a table corresponding to different erase count ranges, the system adapts the erase operation parameters to the actual state of the memory cells, preventing both insufficient erasure and excessive damage
2Productivity
If the erase voltage initial value is increased to improve erasure effectiveness, then the erasure speed is improved, but the read errors increase
Solution Approach 1:
The patent adjusts the initial voltage value of the erase voltage based on the memory cell block's erase count. By storing different initial voltage values in a table corresponding to different erase count ranges, the system optimizes the balance between erasure effectiveness and read error prevention, using higher initial voltages for blocks needing stronger erasure and lower initial voltages for blocks closer to end-of-life
3Device complexity
If a fixed erase voltage setting is used to simplify control, then the device complexity is reduced, but the storage stability deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal erase voltage parameters (pulse time and initial voltage value) in a table for different erase count ranges before actual erase operations. This allows the controller to quickly retrieve and apply appropriate parameters without complex real-time calculations, maintaining simplicity while ensuring stability
Solution Approach 2:
The patent implements feedback by monitoring the erase count of memory cell blocks and using this information to determine appropriate erase voltage parameters. The erase count serves as feedback about the memory block's state, allowing the system to adaptively adjust parameters to maintain optimal erase performance throughout the memory device's lifespan
Data Source
AI summary
According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.