Memory Controller Error Correction for Non-Volatile Memory Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In rewritable non-volatile memory modules, programming errors in upper physical pages can affect lower physical pages on the same word line, requiring multiple error correcting codes to protect data effectively, but existing methods fail to adequately address the issue of error propagation across bit lines.
Innovation Solution
A data protecting method that generates a first error correcting code using data from specific memory cells on different bit and word lines, where only one memory cell on each bit line is used to generate the code, allowing for effective error correction across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple error correcting codes are used to protect data in lower physical pages, then data protection reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error protection mechanism by creating separate error correcting codes for different physical pages. Specifically, it generates a first error correcting code for upper physical pages and a second error correcting code for lower physical pages, allowing independent error correction for each segment without requiring complex multi-layer coding schemes
Solution Approach 2:
The patent introduces an intermediary structure where specific memory cells on bit lines serve as dedicated error correction sources. These memory cells contain data used to generate error correcting codes without storing the actual user data, acting as intermediaries between the user data and the error correction mechanism
2Ease of manufacture
If data is stored in lower physical pages first, then programming sequence requirements are satisfied, but error propagation risk increases
Solution Approach 1:
The patent divides the memory structure into distinct segments with independent error protection: upper physical pages with their own error correcting code and lower physical pages with their own error correcting code. This segmentation prevents errors in one segment from propagating to another, addressing the harmful effect while maintaining the required programming sequence
Solution Approach 2:
The patent performs preliminary error correction preparation by generating error correcting codes for lower physical pages before the actual programming operation. This preliminary action ensures that error correction capability is already in place when programming occurs, reducing the risk of error propagation during the programming process
Data Source
AI summary
A data protecting method, a memory storage device, and a memory controller are provided for a rewritable non-volatile memory module. The data protecting method includes: generating a first error correcting code by using data stored in first memory cells of a plurality of memory cells. The first memory cells are located on first word lines and first bit lines. Among the memory cells located on each of the first bit lines, only one of the memory cells stores the data used to generate the first error correcting code. Accordingly, the data in the memory cells is efficiently protected.