Memory Controller Error Correction and Data Reversal

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Solution Overview

Problem

Existing memory controllers fail to sufficiently reduce error frequency in memory cells due to lack of re-writing for cells with no errors, leading to potential new errors from repetitive access and aging deterioration.

Innovation Solution

A memory controller that includes a reading unit, error detection/correction unit, data reversing unit, and writing unit to read, correct, and reverse information bits, and write the corrected and reversed data in memory cells, thereby addressing the issue of error occurrence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If re-writing is performed only on memory cells with errors, then error correction is achieved, but memory cells with no errors still deteriorate due to repetitive access and aging

Engineering Contradiction:
Improveerror correctionVSAvoidmemory cell lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent applies preliminary action by performing re-writing on memory cells before actual errors occur. The controller identifies memory cells that have not been rewritten recently and proactively rewrites data in these cells during refresh operations, preventing deterioration from accumulating to the point of error before corrective action is taken.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by making re-writing a continuous process rather than a periodic one triggered only by errors. The controller continuously monitors memory cell states and maintains re-writing operations at intervals shorter than the deterioration cycle, ensuring memory cells are constantly refreshed before aging can cause errors.

Inventive Principle:
Principle #20Continuity of useful action

2Duration of action of stationary object

If re-writing is performed on all memory cells including those with no errors, then deterioration is reduced, but unnecessary writing operations increase

Engineering Contradiction:
Improvememory cell lifespanVSAvoidrefresh operation efficiency
Core Design Contradiction:
Duration of action of stationary objectVSProductivity

Solution Approach 1:

The patent applies local quality by treating different memory cells differently based on their individual states. The controller tracks which cells have been recently rewritten and which have not, then selectively applies re-writing only to cells that need it. This prevents unnecessary writing operations on cells that are already in good state while ensuring cells that are deteriorating receive attention.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3211536B1Memory controller, memory system, and memory controller control method
Publication Date: 2019.09.04 SONY GROUP CORP
  • EP3211536B1 patent drawingFigure 1
  • EP3211536B1 patent drawingFigure 2
  • EP3211536B1 patent drawingFigure 3

AI summary

[Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.