Memory Controller Error Correction Algorithm Selection

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Solution Overview

Problem

Current memory systems face limitations in flexibility and reliability due to error correction algorithms being optimized for specific DRAM bit-widths, making it difficult to accommodate changes in DIMM types over time or during production, especially when systems need to accept multiple types of DIMMs differentiated by DRAM bit-widths.

Innovation Solution

A memory controller with error correction logic capable of selecting and implementing multiple error correction algorithms based on the organization of the memory, including configurations with both four-bit-wide and eight-bit-wide DRAMs, and adaptable to changes in DIMM types, using a table to store information about each rank's bit-width and employing algorithms like Reed-Solomon for optimal error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the error correction algorithm is optimized for a specific DRAM bit-width, then the reliability of the memory system is improved, but the adaptability to different DIMM types is reduced

Engineering Contradiction:

Improveerror correction capabilityVSAvoidsupport for multiple DIMM types

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The memory controller dynamically selects and switches between different error correction algorithms based on the detected DRAM bit-width configuration. The system transitions from a static, fixed algorithm to a dynamic, adaptable algorithm selection mechanism that responds to memory organization changes in real-time

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of algorithm selection based on the DRAM bit-width configuration. By detecting whether the system uses 4-bit or 8-bit DRAMs and selecting the appropriate algorithm accordingly, the system adapts to different memory configurations without hardware changes

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the memory controller is designed for a specific DIMM type, then the error correction performance is optimized, but the flexibility to replace DIMMs is reduced

Engineering Contradiction:

Improveerror correction performanceVSAvoidDIMM replacement flexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The memory controller is designed with multi-functionality to support multiple DIMM types (4-bit and 8-bit DRAMs) through a single unified controller that can adapt its error correction algorithm selection based on the detected memory configuration, eliminating the need for separate controllers for different DIMM types

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If multiple error correction algorithms are implemented, then the adaptability to different memory configurations is improved, but the device complexity increases

Engineering Contradiction:

Improvememory configuration compatibilityVSAvoiderror correction logic complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The error correction logic is segmented into multiple dedicated algorithms, each optimized for specific DRAM bit-width configurations. Rather than implementing a single complex adaptive algorithm, the system divides the error correction functionality into separate, specialized algorithms that can be selectively applied based on memory configuration

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7975205B2Error correction algorithm selection based upon memory organization

Publication Date: 2011.07.05 HEWLETT PACKARD ENTERPRISE DEV LP

AI summary

A method is provided for implementing at least one of a number of error correction algorithms operable on a memory. In the method, each of the error correction algorithms is provided. At least one of the error correction algorithms is then selected based on the organization of the memory. At least one error in the memory is corrected using the selected error correction algorithm.