Memory Controller Dynamic Error Correction Code Sizing
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Solution Overview
Problem
Existing memory systems lack the flexibility to adjust error correction capabilities dynamically, which can lead to suboptimal performance in varying system environments.
Innovation Solution
A memory system with a memory controller that can adjust the size of the error correction code based on setting signals, allowing for flexible error correction operations. This system includes multiple memory modules, module controllers, and interface circuits that can operate in normal and extended modes to optimize error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the error correction code size is increased to improve error correction capability, then the reliability is improved, but the device complexity and resource consumption increase
Solution Approach 1:
The patent implements dynamic adjustment of error correction code size based on system operating mode. In normal mode, a first error correction code size is used, while in extended mode, a second (larger) error correction code size is used. This allows the system to adapt the error correction capability to match the actual performance requirements, avoiding unnecessary resource consumption in normal operations while providing enhanced protection when needed.
Solution Approach 2:
The system changes the parameter of error correction code size according to the operating mode. The memory controller adjusts the code size parameter dynamically - using a smaller parameter value in normal mode and a larger parameter value in extended mode. This parameter change enables the system to optimize the balance between reliability and device complexity based on actual operational needs.
2Reliability
If the error correction code size is increased to improve error correction capability, then the reliability is improved, but the storage capacity for user data decreases
Solution Approach 1:
The system dynamically adjusts the error correction code size based on the operating mode to optimize the balance between reliability and storage capacity. In normal mode, the system uses a smaller error correction code size, maximizing the available storage capacity for user data. When extended mode is activated, the system switches to a larger error correction code size to enhance reliability, temporarily reducing the available user data storage capacity.
Solution Approach 2:
The error correction code size parameter is changed according to the operating mode requirements. By changing this parameter dynamically, the system can allocate more resources to user data storage when high reliability is not critical, and allocate more resources to error correction when reliability is the priority, thus optimizing the trade-off between these two competing requirements.
3Reliability
If the memory system operates in extended mode to provide high-performance error correction, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The memory system implements dynamic operational modes that can be switched between normal mode and extended mode. This dynamic configuration allows the system to adjust its complexity level based on requirements. The controller manages the switching between modes, enabling high-performance error correction when needed while maintaining simpler operation during normal use, thus optimizing the balance between reliability and device complexity.
Data Source
AI summary
A memory system includes a plurality of memory modules; a plurality of module controllers configured to respectively control the plurality of memory modules; and a plurality of interface circuits configured to interface the plurality of memory modules with the plurality of module controllers, wherein, according to a setting signal, at least one target interface circuit is configured to interface a target module controller among the plurality of module controllers with a target memory module among the plurality of modules, or interfaces other module controllers different from the target module controller with the target memory module.