Memory Controller Error Address Filtering Circuit
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Solution Overview
Problem
Existing memory systems face challenges in preventing uncorrectable errors due to correctable errors caused by noise, which can lead to system downtime and frequent memory replacements.
Innovation Solution
A processor with a memory controller that includes an address-filter circuit, counter, area-information-output circuit, and request issuing circuit to identify and manage correctable errors, preventing overlapping access operations and reducing noise-induced errors by re-routing access requests to adjacent storage areas with a time gap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory controller continuously monitors and corrects errors in real-time, then error detection capability is improved, but system complexity and processing overhead increase
Solution Approach 1:
The error monitoring function is segmented into dedicated components: an address-filter circuit that extracts error addresses from read responses, and a counter that specifically counts errors per address. This segmentation separates error detection from general memory control, improving detection precision without significantly increasing overall system complexity.
Solution Approach 2:
An address-filter circuit is introduced as an intermediary component between the memory controller and the error monitoring logic. This intermediary selectively filters and processes only error-containing addresses, enabling precise error detection while keeping the main controller simple and efficient.
2Measurement precision
If access operations are performed frequently to monitor errors, then error monitoring accuracy is improved, but noise-induced errors may increase due to overlapping access operations
Solution Approach 1:
The system performs preliminary error detection by monitoring read responses for error flags before initiating corrective access operations. This preliminary detection allows the system to identify error-prone addresses and apply mitigation strategies proactively, preventing noise-induced errors from occurring in the first place.
Solution Approach 2:
The counter mechanism provides a buffer by tracking error frequencies over time before triggering access operations. This cushioning approach prevents premature or excessive access operations that could be triggered by transient noise, while still enabling timely intervention when genuine error patterns emerge.
3Reliability
If the system replaces memory frequently to prevent uncorrectable errors, then system reliability is improved, but productivity and operational continuity deteriorate
Solution Approach 1:
The system implements feedback through the counter that continuously monitors error frequencies and triggers access operations only when error counts exceed a threshold. This feedback mechanism enables the system to maintain reliability by intervening only when necessary, avoiding unnecessary memory replacements that would disrupt operational continuity.
Solution Approach 2:
The system changes the operational parameter from frequent preventive replacement to threshold-based selective access. By monitoring error count parameters and triggering operations only when thresholds are exceeded, the system maintains reliability while minimizing disruptions to productivity and operational continuity.
4Reliability
If the memory controller implements comprehensive error correction mechanisms, then data integrity is improved, but processing time and system performance worsen
Solution Approach 1:
The system applies partial error correction by monitoring only read operations for errors and triggering corrective access operations selectively based on error frequency thresholds. This partial action approach maintains data integrity for the most critical operations while avoiding the time overhead of comprehensive correction on all memory operations.
Data Source
AI summary
A processor includes a memory-controller that controls an access to a memory which includes through electrode groups and a memory chip including a storage areas connected to each of the through-electrode groups including through-electrodes, and that includes an address-filter circuit that outputs an access address included in a read access request of reading data from the memory, as an error address, a counter that includes counters corresponding to the through-electrode groups and updates a counter value of the counter corresponding to the through-electrode group connected to the storage area indicated by the received error address, a first circuit that outputs area information indicating the storage area connected to the through-electrode group corresponding to the counter having a counter value which is greater than a predetermined value, and a second circuit that outputs an access request to the storage area indicated by the area information output from the first circuit.