Memory Controller Error Masking for Near-Threshold Correction

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Solution Overview

Problem

As memory device capacity increases, it becomes challenging to fabricate devices without defective memory cells, and existing error correction methods are inadequate for handling errors close to the threshold of correctable errors, leading to potential failure in error correction operations.

Innovation Solution

A memory system that compresses data and generates an error mask pattern when error bits are between specific threshold values, updating the parity bit and writing the compressed data along with compression and pattern information to mask and correct errors effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction is performed using conventional methods with fixed thresholds, then simple error cases can be corrected, but error cases near the threshold of correctable errors fail to be corrected reliably

Engineering Contradiction:
Improveerror correction reliabilityVSAvoiderror correction process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamic threshold adjustment by determining whether to perform compression based on the number of error bits detected. When error bits are between first and second thresholds, compression is performed; otherwise, conventional correction is used. This dynamic decision-making process adapts the correction strategy to the specific error condition, improving reliability for near-threshold cases while maintaining simplicity for obvious cases.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of data representation by compressing data when error bits are detected within a specific range. This parameter change (from uncompressed to compressed format) alters how the data is processed and corrected, enabling reliable correction of error cases that would otherwise fail with conventional fixed-threshold methods.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If data compression is performed to improve error correction, then error masking effectiveness increases, but processing time and computational complexity increase

Engineering Contradiction:
Improveerror correction performanceVSAvoiddata processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing compression only for data containing error bits within the specific threshold range, rather than compressing all data. This selective approach improves error correction performance where needed while avoiding the time penalty of universal compression, thus resolving the contradiction between reliability improvement and processing time.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system dynamically decides whether to compress data based on the detected number of error bits. This dynamic selection ensures that compression (and its associated time cost) is applied only when necessary to improve correction reliability, rather than being a static operation on all data.

Inventive Principle:
Principle #15Dynamics

3Ease of manufacture

If redundancy memory cells are added to repair defective cells, then manufacturing yield improves, but device complexity and area increase

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidmemory chip area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent changes the parameter of data density by compressing data to concentrate error bits in specific regions. This allows more efficient use of existing memory resources and reduces the need for additional redundancy cells, thereby improving manufacturing yield without proportionally increasing chip area.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11003531B2Memory system and operating method thereof
Publication Date: 2021.05.11 MIMIRIP LLC
  • US11003531B2 patent drawing
  • US11003531B2 patent drawing
  • US11003531B2 patent drawing

AI summary

A memory system includes: a memory device, including a plurality of memory cells, suitable for reading and writing data with a parity bit on a basis of a page; and a memory controller suitable for obtaining an error mask pattern based on compressed data when a number of error bits detected based on the data and the parity bit is equal to or less than a first threshold value and greater than a second threshold value, and controlling to write the compressed data, the parity bit updated based on the compressed data in which the error mask pattern is reflected, compression information on the compressed data and pattern information on the error mask pattern to the page.