Memory Controller Error Notification for Host Workload Reduction
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Solution Overview
Problem
NAND-type flash memory systems face increased workload on host apparatuses due to rising error bits during multiple read operations, necessitating frequent refresh processing to correct errors, which is resource-intensive and inefficient.
Innovation Solution
A memory system with an integrated ECC circuit and controller that communicates error correction results to the host through a serial interface, allowing the host to set a threshold for error detection and notification, thereby reducing the host's workload by enabling targeted refresh operations based on error bit counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host apparatus performs frequent refresh processing to correct error bits during multiple read operations, then data reliability is improved, but the workload and resource consumption of the host apparatus increases
Solution Approach 1:
The memory device autonomously monitors its own error bits during read operations and automatically performs refresh processing when error bits exceed a threshold, eliminating the need for the host apparatus to continuously check and manage error correction, thus reducing host workload while maintaining data reliability
Solution Approach 2:
The system implements a feedback mechanism where the memory device monitors error bit counts during read operations and uses this information to trigger refresh operations when thresholds are exceeded, creating a closed-loop error management system that adapts to actual memory conditions
2Reliability
If the host apparatus continuously monitors and corrects error bits, then data integrity is maintained, but system efficiency and resource utilization deteriorate
Solution Approach 1:
Instead of continuous monitoring, the system performs error bit monitoring and refresh operations periodically based on read operation counts and error threshold comparisons, reducing system overhead while maintaining data integrity through targeted refresh cycles
Solution Approach 2:
The memory device performs error correction in advance during read operations before data is used by the host, and proactively refreshes memory blocks when error thresholds are approached, preventing errors from affecting data integrity rather than reacting to failures after they occur
Data Source
AI summary
A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.