Memory Controller Error Position Refinement for Flash Reliability
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Solution Overview
Problem
As the number of bits stored per memory cell increases in flash memory devices, the read margin of each memory cell decreases, leading to an increase in data errors, which existing error correction mechanisms struggle to effectively address.
Innovation Solution
The proposed solution involves an operation method of a memory controller that stores write data in a first area of the memory device, extracts error position information, stores this information in a second area, and uses it to refine read data, perform soft decision decoding, and output corrected data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored per memory cell is increased to increase storage capacity, then the storage capacity of the flash memory device increases, but the read margin of each memory cell decreases leading to increased data errors
Solution Approach 1:
The patent segments the read operation into multiple stages: initial read, error detection, error position identification, and targeted re-reading. By dividing the read process into discrete steps and focusing correction efforts on specific error positions rather than treating all data uniformly, the system can effectively handle higher bit-density storage while maintaining reliability through systematic error management
Solution Approach 2:
The patent performs preliminary error detection and error position identification before final data correction. By conducting initial reads and identifying error positions in advance, the system prepares correction strategies beforehand, allowing the main read operation to be optimized with pre-acquired error information, thus maintaining high storage capacity while ensuring data integrity
2Reliability
If existing error correction mechanisms are used to address data errors, then some errors can be corrected, but the increasing number of errors due to higher bit density exceeds the correction capacity
Solution Approach 1:
The patent applies local quality by focusing error correction resources on specific error positions rather than uniformly processing all data. By identifying exact error locations and applying correction only where needed through targeted re-reads and refined error correction algorithms, the system maximizes correction effectiveness without being overwhelmed by the total number of errors, enabling reliable operation at higher bit densities
Solution Approach 2:
The patent implements feedback mechanisms where error detection results from initial reads are used to guide subsequent correction operations. The system continuously monitors error positions, adjusts re-reading strategies based on detected error patterns, and refines correction approaches using feedback from each read cycle, creating an adaptive error correction system that scales with increasing bit density
Data Source
AI summary
Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.