Memory Controller Escalation for Address Conflict Resolution
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Solution Overview
Problem
In modern mobile electronic devices, address conflicts between memory requests can lead to underflow issues due to the slow progress of best effort requests, which can cause delays in real-time read requests accessing shared memory.
Innovation Solution
A memory controller system with a system cache and miss queue that uses QoS attributes to escalate or bypass best effort requests based on their status, allowing real-time requests to prioritize and expedite data retrieval by setting push attributes and enqueuing requests with higher QoS levels to bypass or push best effort requests through the memory controller switch and channel units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a best effort read request is allocated in the system cache, then the system cache can store more data, but the request progresses slowly due to low priority, causing underflow issues
Solution Approach 1:
The system dynamically changes the QoS parameter of requests based on their type and system state. Real-time requests are assigned high priority QoS attributes while best effort requests receive low priority attributes, allowing the system to adjust processing speed without changing the underlying cache storage capacity.
Solution Approach 2:
The memory controller implements dynamic priority assignment where request handling characteristics change based on real-time conditions. The system can escalate best effort requests to higher priorities when address conflicts are detected, making the system adaptable to varying workload conditions.
2Speed
If a real-time read request is received with an address conflict, then data retrieval can be expedited, but the slow progress of the best effort request causes delays
Solution Approach 1:
The memory controller introduces an intermediary arbitration mechanism that manages address conflicts between requests. When a real-time request conflicts with a best effort request, the intermediary escalates the best effort request's priority, allowing the real-time request to proceed without delay while ensuring the best effort request eventually completes.
Solution Approach 2:
The system performs preliminary detection of address conflicts when real-time requests are received. By identifying conflicts before they cause delays, the system can proactively escalate best effort requests to higher priorities, preventing underflow issues before they occur.
3Productivity
If multiple agents access memory via the memory controller, then memory utilization increases, but address conflicts between requests occur
Solution Approach 1:
The memory controller applies different quality attributes (QoS levels) to different requests based on their origin and type. Real-time requests from agents like displays receive high priority treatment, while best effort requests from agents like scalers receive lower priority, allowing simultaneous access without mutual interference.
Solution Approach 2:
The system segments the memory access stream into different priority classes using QoS attributes. By dividing requests into real-time and best effort categories, the system can handle multiple agent requests concurrently while maintaining reliability through priority-based arbitration when address conflicts occur.
Data Source
AI summary
Techniques for escalating a real time agent's request that has an address conflict with a best effort agent's request. A best effort request can be allocated in a memory controller cache but can progress slowly in the memory system due to its low priority. Therefore, when a real time request has an address conflict with an older best effort request, the best effort request can be escalated if it is still pending when the real time request is received at the memory controller cache. Escalating the best effort request can include setting the push attribute of the best effort request or sending another request with a push attribute to bypass or push the best effort request.