Memory Controller Event Counter for Asymmetric Block Synchronization
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Solution Overview
Problem
Conventional memory control systems face challenges in efficiently managing write and read operations due to differences in block sizes and numbers for writing and reading, leading to improper chase control and increased time required for image data processing in imaging devices.
Innovation Solution
A memory control apparatus and method that divides image data into multiple blocks, with a writing unit and a reading unit issuing events upon completion of block operations, and a controller that increments or decrements a count value to control write and read requests based on these events, ensuring proper chase control and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory control is used with different block sizes and numbers for writing and reading, then the memory operations can proceed independently, but chase control cannot be properly performed leading to synchronization issues
Solution Approach 1:
The patent implements feedback mechanisms through event counters that track write and read operations. The controller monitors write events (incrementing the counter) and read events (decrementing the counter) to dynamically adjust permission signals, ensuring that read operations never exceed available written data while maintaining high operational throughput.
Solution Approach 2:
The patent introduces an intermediary event counter mechanism between the writing and reading units. This counter acts as a mediator that coordinates the asymmetric block operations by tracking the difference between written and read blocks, allowing independent operation while maintaining synchronization through the permission signal controlled by the counter value.
2Loss of time
If image data is processed immediately after writing to reduce time, then processing speed increases, but the risk of readout address overtaking writing address increases
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and controlling the permission signals based on the event counter value before actual read operations occur. This ensures that readout addresses are prevented from overtaking writing addresses in advance, allowing immediate processing while maintaining address synchronization through proactive control.
Solution Approach 2:
The permission signal mechanism provides continuous feedback control where the controller monitors the event counter and dynamically adjusts read/write permissions. This feedback loop ensures that even when processing occurs immediately after writing, the address synchronization is maintained by preventing read operations when the counter indicates insufficient written data.
3Productivity
If block-based processing is implemented to improve memory control, then operation efficiency improves, but the complexity of coordinating different block sizes and numbers increases
Solution Approach 1:
The patent handles different block sizes and numbers by changing the parameter interpretation in the event counter. Rather than requiring complex coordination logic, the system simply increments or decrements the counter based on individual block completion events, allowing the same simple counter mechanism to accommodate varying block parameters without increasing structural complexity.
Data Source
AI summary
A memory control apparatus including: a writing unit configured to output a write request for writing to a memory and issues a first event every time a write operation of each of the first blocks is completed; a reading unit configured to output a readout request for reading of image data that has been written to the memory by the writing unit and issues a second event every time a readout operation of the second block is completed; and a controller that performs a process of incrementing a count value in response to the first event, performs a process of decrementing the count value in response to the second event, and controls whether to permit the write request and the readout request, respectively, based on the count value.