Memory Controller Extrinsic Bitline Defect Detection

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Solution Overview

Problem

Existing memory sub-systems face inefficiencies due to the inability to effectively identify and prevent writes to memory portions with extrinsic bitline defects, leading to repeated NDEP operations that consume system resources without repairing data.

Innovation Solution

A memory controller is configured to track the frequency of memory operations on memory portions and measure the bit error rate, marking portions with excessive operations or high error rates as bad to prevent further writes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If NDEP operations are repeatedly performed on memory portions with extrinsic bitline defects, then the system attempts to repair data, but system resources are consumed without actual repair occurring

Engineering Contradiction:
Improvedata repair effectivenessVSAvoidsystem resource consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by performing NDEP operations and tracking their frequency before definitively marking memory portions as bad. The system proactively monitors operation counts and bit error rates, and only after exceeding thresholds does it prevent further writes. This preliminary monitoring approach allows the system to identify defective portions early while avoiding unnecessary operations on clearly defective memory, thus balancing repair attempts with resource conservation.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the system continues performing memory operations on defective portions, then operational continuity is maintained, but unnecessary operations waste time and resources

Engineering Contradiction:
Improveoperational continuityVSAvoidwasted operation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements feedback by continuously monitoring the frequency of NDEP operations and measuring bit error rates on memory portions. This feedback mechanism allows the system to adapt its behavior dynamically - when operation frequency exceeds a first threshold or bit error rate exceeds a second threshold, the system responds by preventing further writes to those portions. This feedback loop ensures operational continuity on healthy memory while automatically eliminating wasteful operations on defective memory, thus resolving the contradiction between maintaining productivity and avoiding time waste.

Inventive Principle:
Principle #23Feedback

3Reliability

If the system performs additional NDEP operations after erasing memory portions, then it attempts to ensure data integrity, but this increases the complexity of memory management

Engineering Contradiction:
Improvedata integrityVSAvoidmemory management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by establishing specific threshold values for NDEP operation frequency and bit error rates that trigger bad block marking. Instead of using complex adaptive algorithms or multiple decision layers, the system uses straightforward parameter comparisons - when operation count exceeds threshold or error rate exceeds threshold, the memory portion is marked bad. This parameter-based approach maintains data integrity through systematic monitoring while keeping the memory management logic relatively simple and easy to implement.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250166718A1Detecting extrinsic bitline defects
Publication Date: 2025.05.22 MICRON TECHNOLOGY INC
  • US20250166718A1 patent drawing
  • US20250166718A1 patent drawing
  • US20250166718A1 patent drawing

AI summary

Aspects of the present disclosure configure a memory sub-system controller to detect extrinsic bitline defects. The controller stores a set of data in a set of memory components and performs a set of memory operations for detecting an empty page in a portion of the set of memory components. The controller determines, based on performing the set of memory operations, that the portion of the set of memory components is associated with an extrinsic bitline defect. The controller, in response to determining that the portion of the set of memory components is associated with the extrinsic bitline defect, prevents write operations to the portion of the set of memory components.