Memory Controller Program Fail Bit Correction
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Solution Overview
Problem
Flash memory systems face reliability issues during read operations due to program fail bits exceeding the maximum allowed number of error correcting code bits, leading to reduced performance and data integrity.
Innovation Solution
A memory system with a controller that performs a second program operation on selected memory cells with program fail bits greater than the maximum allowed ECC bits, increasing threshold voltage distributions to reduce program fail bits and enhance read operation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first program operation is performed on memory cells, then data is programmed into the memory cells, but program fail bits may exceed the maximum allowed ECC bits, reducing read operation reliability
Solution Approach 1:
The patent performs a program fail bit detection operation immediately after the first program operation to identify memory cells that failed to program correctly. This preliminary detection allows for targeted re-programming of only those specific memory cells that need correction, rather than re-programming all memory cells or accepting the failure.
Solution Approach 2:
The patent changes the threshold voltage distribution parameter by performing a second program operation on selected memory cells that have program fail bits. This parameter change adjusts the threshold voltage to move it into the correct program state range, thereby reducing program fail bits and improving read operation reliability.
2Reliability
If program fail bits exceed the maximum allowed ECC bits, then data integrity is compromised, but performing a second program operation on all memory cells increases operation complexity
Solution Approach 1:
The patent applies local quality by performing the second program operation only on selected memory cells that have program fail bits, rather than on all memory cells. This localized approach maintains data integrity for affected cells while minimizing unnecessary operations on cells that are already correctly programmed, thereby reducing overall operation complexity.
Solution Approach 2:
The patent segments the memory cell population into two groups: memory cells that require re-programming (those with program fail bits) and memory cells that are already correctly programmed. This segmentation allows the controller to apply different operations to different segments, improving efficiency and reducing complexity compared to uniform processing of all cells.
3Reliability
If a second program operation is performed on selected memory cells, then program fail bits are reduced, but additional programming time is required
Solution Approach 1:
The patent applies partial action by performing the second program operation only on the subset of memory cells that have program fail bits, rather than on all memory cells. This partial re-programming approach reduces the total programming time required compared to a full re-program operation, while still achieving the goal of reducing program fail bits below the ECC threshold.
Solution Approach 2:
The patent uses feedback from the program fail bit detection operation to control whether a second program operation is performed. The detection results provide feedback about which memory cells need correction, allowing the system to dynamically adjust the programming process and avoid unnecessary re-programming of cells that are already correct, thereby minimizing additional programming time.
Data Source
AI summary
Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a semiconductor memory device including a plurality of memory cells to be programmed to an erase state and a plurality of program state; and a controller configured to control the semiconductor memory device to perform a program operation or a read operation in response to a request of a host. The controller may control the semiconductor memory device such that when, after a first program operation of the program operation has been performed, a number of program fail bits of the plurality of memory cells is greater than a maximum allowed number of ECC bits, a second program operation is performed on selected memory cells of the plurality of memory cells.