Memory Controller Fail Bit Correction via Spare Data Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in efficiently managing fail bits and reducing the number of refresh operations, which can lead to increased wear and decreased reliability, especially in multi-value storage scenarios.
Innovation Solution
A memory system that includes a nonvolatile semiconductor storage device and a memory controller, which collectively stores and manages spare data across pages to correct fail bits and reduce the frequency of refresh operations, thereby extending the lifespan of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently to maintain data integrity, then reliability is improved, but memory cell wear increases and lifespan decreases
Solution Approach 1:
The patent performs preliminary detection of fail bits during patrol read operations and stores correction data in advance. When data is subsequently read, the stored correction data is applied immediately without requiring a refresh operation, thus preventing memory cell wear while maintaining data integrity.
Solution Approach 2:
The patent extracts and separates the correction data for fail bits from the main data storage structure. By storing correction data in a dedicated spare region and applying it during read operations, the system avoids the need for frequent refresh operations that would otherwise be required to maintain data integrity.
2Reliability
If patrol read operations are performed to detect fail bits, then reliability is improved, but the number of read operations increases
Solution Approach 1:
The patent performs preliminary detection of fail bits during background patrol read operations and stores correction data in advance. This allows the main read operations to proceed efficiently without needing to perform additional detection, as the correction data is already prepared and stored in the spare region.
Solution Approach 2:
The system performs self-diagnosis through patrol read operations to detect fail bits and automatically generates and stores correction data. This self-service mechanism maintains reliability without requiring external intervention or significantly impacting overall system productivity.
3Reliability
If correction data is stored for each page, then fail bit correction capability is improved, but memory space consumption increases
Solution Approach 1:
The patent creates an association between spare regions and multiple main pages, allowing a single spare region to store correction data that can serve multiple pages. This multi-functional approach improves correction capability while reducing the total amount of memory space required for spare data compared to dedicating a separate spare region to each page.
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.