Semiconductor Memory Controller Parallel Data Recovery
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing program failures, leading to increased operation time and power consumption due to the need for extensive post-processing operations and re-programming of failed data.
Innovation Solution
A controller system that includes a processor for post-processing operations, a fail controller to request and retrieve recovered data from a page buffer, and a memory controller to store the recovered data in a designated recovery address, allowing for simultaneous recovery and storage while performing post-processing, thereby reducing the processor's load and increasing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor performs both post-processing operations and data recovery operations, then the processor can handle all tasks, but the operation speed decreases and power consumption increases
Solution Approach 1:
The controller is divided into two independent functional modules: a processor dedicated to post-processing operations (bad block management, address translation) and a fail controller dedicated to data recovery operations. This segmentation allows parallel execution of tasks, improving operation speed and reducing power consumption by avoiding sequential processing bottlenecks.
Solution Approach 2:
The fail controller autonomously handles data recovery operations including transmitting recovery commands to the semiconductor memory device, receiving recovered data, and storing it in the buffer memory without requiring processor intervention. This self-service capability frees the processor to focus solely on post-processing tasks, enhancing overall system efficiency.
2Reliability
If the processor performs extensive post-processing operations on program failures, then data integrity is maintained, but the operation time increases
Solution Approach 1:
The fail controller proactively monitors program operations and immediately initiates data recovery when a program failure is detected, before the failed data is permanently lost. This preliminary action ensures data integrity is maintained while minimizing the time the processor needs to spend on post-processing, as recovery begins automatically without waiting for processor intervention.
3Device complexity
If the processor handles both post-processing and data recovery tasks, then all functions are centralized, but the system complexity increases
Solution Approach 1:
The controller architecture is segmented into distinct functional units: the processor for post-processing and the fail controller for data recovery. While this increases structural complexity, it dramatically improves operation efficiency through parallel processing, demonstrating that controlled complexity can yield significant performance benefits.
Data Source
AI summary
There are provided an electronic device, and more particularly, to a controller of a semiconductor memory device with an increased operation speed and a method of operating the same. The method of operating the controller configured to control the semiconductor memory device includes obtaining a recovery address in which recovered data stored in a page buffer of the semiconductor memory device in which the program fail is generated is to be stored, transmitting a recovery command requesting the semiconductor memory device to transmit the recovered data to the semiconductor memory device, and storing the recovered data in the recovery address. The obtaining of the recovery address, the transmitting of the recovery command, and the storing of the recovered data in the recovery address are simultaneously performed while a post-processing operation is performed on the program fail.