Memory Controller Fast Timing Reacquisition for Rank Switching
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Solution Overview
Problem
Existing memory systems face inefficiencies in power management due to idle ranks drawing power, and existing feedback-control loops for timing updates are either power-consuming or too slow, making them unsuitable for rapid rank switching.
Innovation Solution
A memory controller performs fast timing reacquisition using a calibration preamble to adjust the delay line, allowing for rapid phase updates and reducing power consumption by shifting timing-control components from memory ranks to the controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If feedback-control loops (PLL or DLL) are used to update timing signals for memory accesses, then timing drift can be compensated, but the updates require many clock cycles and consume too much power or are too slow for rapid rank switching
Solution Approach 1:
The patent applies preliminary action by performing fast timing reacquisition during the read operation itself. The memory controller uses the calibration preamble received during the read operation to quickly adjust the delay line and compensate for timing drift, rather than waiting for slow feedback-control loops to complete their updates after the fact.
Solution Approach 2:
The patent implements skipping by bypassing the slow feedback-control loop update process entirely during rank switching. Instead of waiting for multiple clock cycles for PLL/DLL updates, the system rushes through timing compensation by directly adjusting the delay line using timing information extracted from the calibration preamble during the ongoing read operation.
2Use of energy by stationary object
If timing-control components (PLL or DLL) are moved from memory ranks to memory controller, then idle power consumption is reduced, but timing updates become slower and less responsive to rapid rank switching
Solution Approach 1:
The patent applies self-service by enabling the memory controller to perform fast timing reacquisition autonomously during read operations. The controller extracts timing information from the calibration preamble and directly adjusts its own delay line without requiring external timing updates from slow feedback-control loops, thus maintaining low idle power while achieving fast timing adaptation.
Solution Approach 2:
The patent implements dynamics by making the timing control system adaptive and responsive to actual operating conditions. The delay line can be dynamically adjusted during read operations based on real-time timing information from the calibration preamble, allowing the system to switch between power-saving mode (idle ranks off) and high-performance mode (fast timing adjustment during active operations).
Data Source
AI summary
Techniques for performing fast timing reacquisition of read timing in a memory controller to support rank switching device are described. During operation, a memory controller receives read data for a read operation, wherein the read data includes a calibration preamble. The memory controller uses the calibration preamble to perform a fast timing reacquisition operation to compensate for a timing drift between a clock path and a data path for the read data. In particular, the memory controller performs the fast timing reacquisition by adjusting a data delay line coupled to a clock path associated with a control loop, wherein the control loop controls a data clock which is used to receive read data at the memory controller.