Unified Memory Controller Fastpath Write Classification

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Solution Overview

Problem

The existing hierarchical memory structure in computer systems faces performance issues due to the difference in speed between volatile and non-volatile memories, leading to inefficient data management and energy consumption, especially when performing frequent input and output operations.

Innovation Solution

A data processing system that classifies processes as critical or non-critical, using a unified memory controller to manage data storage by providing fastpath or slowpath write signals to either a first or second non-volatile memory based on classification, optimizing write operations and energy usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a hierarchical memory structure with volatile and non-volatile memory is used, then data stability is improved, but system performance deteriorates due to speed differences and block access limitations

Engineering Contradiction:
Improvedata stabilityVSAvoidsystem performance
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The invention segments the memory system into two distinct paths: a fastpath for critical processes that requires high speed and synchronous access, and a slowpath for non-critical processes that can tolerate asynchronous access. This segmentation allows each path to be optimized independently, resolving the contradiction between data stability and system performance by providing appropriate access methods for different data types.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention dynamically classifies processes as either critical or non-critical based on their specific requirements, and routes them through appropriate paths. This dynamic adaptation allows the system to optimize performance for each process while maintaining data stability, rather than using a static memory hierarchy that treats all data uniformly.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If capacities of main memory and secondary storage device are increased, then data storage capability is improved, but energy consumption increases

Engineering Contradiction:
Improvedata storage capacityVSAvoidenergy consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The invention applies local quality by providing different access characteristics to different portions of stored data based on their criticality. Critical data accessed through the fastpath receives high-speed synchronous access, while non-critical data accessed through the slowpath uses asynchronous transfer. This allows the system to maintain large storage capacity while consuming less energy by not providing high-speed access to all data uniformly.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention changes the access mode parameter from a single unified mode to two distinct modes: synchronous access for critical processes and asynchronous access for non-critical processes. This parameter change enables the system to optimize energy consumption by matching the access speed and protocol to the actual requirements of each data type, rather than maintaining high-speed synchronous access for all data.

Inventive Principle:
Principle #35Parameter changes

3Speed

If fastpath write operation is used for critical processes, then write speed is improved, but system complexity increases due to dual path management

Engineering Contradiction:
Improvewrite speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The invention introduces a process classification mechanism that acts as an intermediary between the application layer and the dual memory paths. This classifier automatically determines whether a process is critical or non-critical and routes it to the appropriate path, thereby managing the system complexity centrally rather than distributing it throughout the entire system. The fastpath provides high write speed for critical processes while the classification mechanism handles the complexity of dual-path management.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If synchronous write request is required for critical processes, then data reliability is improved, but processing time increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The invention segments the write operation into two distinct protocols: synchronous write for critical processes that require data reliability, and asynchronous write for non-critical processes that can tolerate delayed confirmation. This segmentation allows critical processes to maintain high reliability through synchronous confirmation while non-critical processes achieve faster processing times through asynchronous transfer, resolving the contradiction between reliability and processing time.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9836220B2Data processing system and method of operating the same
Publication Date: 2017.12.05 SAMSUNG ELECTRONICS CO LTD
  • US9836220B2 patent drawing
  • US9836220B2 patent drawing
  • US9836220B2 patent drawing

AI summary

A method of operating a data processing system includes transmitting process information indicating that a first process is classified as a critical process or a non-critical process to a kernel area, wherein the process information is generated in an application area, and the application area and the kernel area define a host. When the first process is classified as a critical process based on the process information, a first fastpath write signal is provided, using the kernel area, to a memory system to perform a fastpath write operation of first data for performing the first process. When the first process is classified as a non-critical process, a first slowpath write signal is provided to the memory system to perform a slowpath write operation of the first data. The fastpath write operation has a higher write speed than the slowpath write operation.