Memory Controller Feedback for CPU Request Throttling
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Solution Overview
Problem
In processor systems, memory access congestion occurs due to overwhelming memory requests from multiple threads, leading to uneven service rates and performance issues, particularly in multi-core systems where multiple CPU cores generate simultaneous memory requests that overwhelm the memory controller.
Innovation Solution
Implementing a feedback mechanism where memory controllers use queue depth and congestion ratios to send signals to CPU cores, allowing them to throttle memory access requests, thereby distributing resources evenly among threads and reducing congestion without requiring inter-memory controller communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple CPU cores generate simultaneous memory requests in a multi-thread environment, then system throughput and processing capability are improved, but memory access congestion occurs at the memory controller
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller monitors its internal queue depth and sends feedback signals to CPU cores. When the queue depth exceeds a threshold, the memory controller signals CPU cores to throttle memory access requests, creating a closed-loop control system that dynamically adjusts request rates to prevent congestion while maintaining high throughput.
Solution Approach 2:
The patent dynamically changes the memory access request rate parameter based on memory controller queue depth. CPU cores adjust their request generation rate in response to feedback signals, transitioning between high-rate and low-rate modes to optimize system throughput while avoiding congestion at the memory controller.
2Device complexity
If memory controllers manage congestion independently without inter-controller communication, then device complexity is reduced, but coordination between multiple memory controllers may be insufficient
Solution Approach 1:
The patent enables each memory controller to independently manage its own congestion by monitoring its internal queue depth and autonomously generating feedback signals to CPU cores. This self-service approach eliminates the need for complex inter-memory controller communication infrastructure while maintaining effective congestion control through localized feedback loops.
Data Source
AI summary
Example methods, apparatus, and articles of manufacture to control generation of memory access requests in processor systems are disclosed. A disclosed example method involves determining at a memory controller whether a memory access queue depth for a memory reference is greater than a first threshold. When the memory access queue depth for the memory reference is greater than the first threshold, an indication is sent to control generation of memory access requests corresponding to the memory reference.