Memory Controller Synchronous Sampling via FIFO Timestamping
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Solution Overview
Problem
In synchronous memory systems, increased processor and peripheral device speeds lead to phase differences between clock and data signals due to propagation delays, causing incorrect data sampling, and existing solutions like phase locked loops (PLL) or feedback loops either fail at certain delay thresholds or require additional silicon area or pins.
Innovation Solution
A processing system with a FIFO buffer, clock module, control signal generation, and counter module that synchronizes data sampling by using a system clock signal and access latency to timestamp read operations, eliminating the need for PLLs and extra pins, allowing for correct sampling regardless of propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of memory devices is increased to match processor speeds, then productivity is improved, but phase differences due to propagation delays increase causing incorrect data sampling
Solution Approach 1:
The patent uses a feedback mechanism where the clock signal from the memory device is fed back to the memory controller through a feedback path. This feedback loop allows the controller to detect the actual phase relationship between clock and data signals and adjust the sampling timing accordingly, ensuring correct data sampling even at high operating speeds where propagation delays are significant
2Reliability
If a phase locked loop (PLL) circuit is used to align clock edges, then data sampling accuracy is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent extracts the essential function of phase alignment from the complex PLL circuitry and implements it through a simplified feedback mechanism using basic logic elements. Instead of using a full PLL, the invention takes out only the necessary phase detection and adjustment functionality, achieving the same reliability improvement with significantly reduced circuit complexity and silicon area
3Reliability
If feedback loops are used to compensate for delays, then data sampling accuracy is improved, but device complexity increases due to additional pins required
Solution Approach 1:
The patent merges the feedback signal path with the existing clock signal path by using the same physical connection for both directions of signal flow. The feedback mechanism is implemented by routing the clock signal from the memory device back to the controller through the existing interface, eliminating the need for separate feedback pins and reducing overall device complexity while maintaining data sampling accuracy
Data Source
AI summary
A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.