Memory Controller Fine Program Timing and Interference Management

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Solution Overview

Problem

Current memory controllers face challenges in efficiently managing foggy and fine program operations across multiple pages, particularly in handling interference and ensuring timely completion of program operations, which can lead to increased probability of program failures.

Innovation Solution

A memory controller with a fine program timer and command controller that records foggy program completion times and outputs dummy program instructions based on elapsed time, allowing for fine program commands to be issued after a threshold is exceeded, and performs dummy program operations on adjacent pages to minimize interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory controller waits for foggy program completion response before issuing fine program command, then program operation reliability is improved, but program operation time is increased

Engineering Contradiction:
Improveprogram operation reliabilityVSAvoidprogram operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory controller issues a fine program command in advance based on a predetermined time threshold from the foggy program start time, before receiving the foggy program completion response. This preliminary action reduces the total program operation time while maintaining reliability through subsequent verification steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory controller receives the foggy program completion response and performs verification to determine whether the fine program operation was successfully completed. This feedback mechanism ensures program operation reliability even when the fine program command is issued in advance.

Inventive Principle:
Principle #23Feedback

2Loss of time

If the memory controller performs fine program operation immediately after foggy program, then program operation time is reduced, but program failure probability is increased due to interference

Engineering Contradiction:
Improveprogram operation timeVSAvoidprogram failure probability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The memory controller performs a dummy program operation on a dummy page in advance before issuing the fine program command. This preliminary action prepares the memory device to reduce interference effects, allowing the fine program to be performed sooner while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy page acts as an intermediary element that absorbs interference effects. By performing a dummy program operation on this separate page first, the memory device is prepared to reduce interference on the actual fine program operation, enabling faster execution without increasing failure probability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the memory controller issues fine program command without timing control, then device complexity is reduced, but manufacturing precision of program operation is degraded

Engineering Contradiction:
Improvecontroller complexityVSAvoidprogram operation precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The memory controller uses a dynamic time threshold that is predetermined based on the number of pages to be programmed. This allows the controller to adapt the timing of the fine program command issuance to different operation scenarios, maintaining precision without requiring overly complex control logic.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11294596B2Memory controller and operating method thereof
Publication Date: 2022.04.05 SK HYNIX INC
  • US11294596B2 patent drawing
  • US11294596B2 patent drawing
  • US11294596B2 patent drawing

AI summary

A memory controller capable of controlling a memory device to perform a fine program operation, based on a time elapsing from a foggy program completion time and a position of a page on which a fine program is performed controls the memory device including a plurality of pages. The memory controller includes: a fine program timer for recording a foggy program completion time at which a foggy program completion response corresponding to a foggy program operation is received from the memory device, and outputting dummy program instruction information, based on an elapsing amount of time from the foggy program completion time; and a command controller for outputting a fine program command, based on the dummy program instruction information.