Memory Controller Firmware Reload Optimization

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Solution Overview

Problem

Current data processing systems face challenges in reducing booting time, particularly when a reset request is received, as they often reload firmware unnecessarily, leading to slowed response times and increased booting times due to improper handling of reset requests.

Innovation Solution

A data processing system with a controller that includes first and second reset circuitries and a firmware load determination circuitry, which determines the reason for a reset request and decides whether to reload firmware from a nonvolatile memory device, thereby optimizing the reset process and reducing booting time by avoiding unnecessary firmware reloads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If firmware is reloaded after every reset request, then system reliability is improved, but booting time increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidbooting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary classification of reset requests into two categories: bit-flip errors (requiring firmware reload) and other errors (not requiring reload). By pre-establishing this classification mechanism, the system avoids unnecessary firmware reloads while maintaining reliability for actual bit-flip cases.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention applies different handling strategies to different types of reset requests. Bit-flip error resets trigger firmware reload, while other reset types do not. This localized differentiation optimizes booting time for common cases without compromising system reliability for critical error cases.

Inventive Principle:
Principle #3Local quality

2Loss of time

If firmware is selectively reloaded based on reset reason, then booting time is reduced, but device complexity increases

Engineering Contradiction:
Improvebooting timeVSAvoidcontroller complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The controller is segmented into distinct functional modules: first reset circuitry for detecting reset requests and classifying error types, second reset circuitry for executing reset operations, and firmware load determination circuitry for deciding whether to reload firmware. This segmentation manages complexity through modular design while enabling selective firmware reloading.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If reset default status is set to bit flip error, then firmware reload determination accuracy is improved, but measurement precision requirements increase

Engineering Contradiction:
Improveerror detection accuracyVSAvoidreset reason detection difficulty
Core Design Contradiction:
Measurement precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The system uses the existing reset default status bit in the status register to indicate bit-flip errors, leveraging an existing system resource for error classification. This self-service approach avoids adding complex detection mechanisms while maintaining accurate identification of bit-flip error cases.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11194587B2Memory system, data processing system and operating method thereof
Publication Date: 2021.12.07 SK HYNIX INC
  • US11194587B2 patent drawing
  • US11194587B2 patent drawing
  • US11194587B2 patent drawing

AI summary

A data processing system comprising: a host; and a memory system comprising a nonvolatile memory device and a controller suitable for controlling the nonvolatile memory device, wherein the controller comprises: a first reset circuitry suitable for loading firmware from the nonvolatile memory device to a volatile memory, and setting a reset default status; a second reset circuitry suitable for determining whether a reason for a reset request coincides with the reset default status, when the reset request is received from the host, and resetting the memory system; and a firmware load determination circuitry suitable for determining whether to reload the firmware by checking the reset default status.