Memory Controller Firmware Software Coordination for DRAM Error Handling
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Solution Overview
Problem
Existing memory fault handling systems face inefficiencies due to the lack of cooperation between hardware and software functions, leading to temporary CPU usage drops and limitations in handling memory errors, especially in high-capacity in-memory computing environments where error frequencies increase, potentially causing system downtime.
Innovation Solution
A memory fault handling system that includes a memory controller, firmware, and software, where the memory controller notifies firmware or software of errors, and the firmware instructs spare memory switching, while the software disables error-prone pages, ensuring coordinated spare memory switching and page offline functions without CPU usage drops or notification limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SW function (page offline) operates first when CEs occur in multiple DRAMs, then the system can prevent uncorrectable errors, but the number of usable memory pages decreases and kernel overhead increases
Solution Approach 1:
The patent applies preliminary action by having the hardware function execute first to copy data to spare DRAM before the software function disables the affected pages. The memory management unit identifies which DRAMs have reached the CE threshold and pre-copies their data to spare DRAMs, so that when the software subsequently disables pages, fewer pages need to be offline and less kernel overhead is generated.
Solution Approach 2:
The patent segments the memory error handling into distinct hardware and software components with specific responsibilities. The hardware function handles the initial data protection by copying to spare DRAM, while the software function handles page management. This segmentation allows each component to optimize its operation and avoid redundant actions that would reduce productivity.
2Reliability
If the HW function operates first to transfer data to spare DRAM, then data protection is improved, but SW cannot respond to memory errors effectively
Solution Approach 1:
The patent introduces the memory management unit as an intermediary between the hardware and software error handling functions. The MMU receives notifications from both the hardware ECC logic and the software, coordinates their actions, and ensures that the hardware function executes first to protect data, followed by the software function to manage pages. This intermediary enables both functions to operate effectively in a coordinated sequence.
Solution Approach 2:
The hardware function performs preliminary data protection by copying data to spare DRAM before the software function executes. This preliminary action ensures data integrity is maintained while still allowing the software to subsequently respond to and manage the memory errors through page offline operations.
3Quantity of substance
If multiple DRAMs are mapped to a single page through memory interleaving, then memory capacity is increased, but CE counting accuracy for individual DRAMs deteriorates
Solution Approach 1:
The patent segments the CE counting function by implementing separate counters in the hardware for each individual DRAM, rather than a single counter for the interleaved page. This segmentation allows precise tracking of CEs in each DRAM independently, enabling the system to identify which specific DRAMs have reached the threshold and require data copying to spare DRAMs.
Solution Approach 2:
The memory management unit acts as an intermediary that receives individual DRAM CE notifications from the hardware and translates them into coordinated actions. The MMU maintains awareness of the interleaving mapping while using the hardware's precise per-DRAM CE counting to determine when data copying is needed, thus preserving both the capacity benefits of interleaving and the precision of individual DRAM monitoring.
Data Source
AI summary
A memory fault handling system includes: a memory controller, firmware, and software. The memory controller has: an error occurrence notification means for, when the occurrence of a memory error is detected, notifying firmware or software of the occurrence of the memory error on the basis of a setting pertaining to a notification recipient. The firmware includes: a notification recipient setting means for setting a notification recipient; and a spare memory switching instruction means for, when a notification indicating the occurrence of a memory error is received from the memory controller, instructing to switch from a memory to a spare memory. The software includes: a disabling instruction means for, when a notification indicating the occurrence of a memory error is received from the memory controller, instructing to cause a page corresponding to the memory in which the memory error has occurred to be disabled.