Memory Controller Interrupt Filtering for Repeated Error Locations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory controllers generate repeated interrupts for the same memory location with errors, leading to an infinite loop and preventing the processor from continuing the execution of instructions, and existing solutions fail to accurately locate and correct these errors.
Innovation Solution
Implement a memory controller with an error detection circuit that generates an interrupt signal only upon the first detection of an error, using a transmission control circuit to store the last error location and compare it with subsequent error locations to prevent repeated interrupts, and a logic circuit to filter interrupts based on address comparisons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller generates an interrupt signal every time an error is detected in information, then the processor can be notified of all errors, but the processor enters an infinite loop and cannot continue executing instructions
Solution Approach 1:
The patent combines the error detection function with a pre-loading mechanism that tracks previously processed instructions. When an error is detected, the system checks whether the erroneous instruction has already been pre-loaded and processed. If so, the interrupt is suppressed, preventing repeated interruptions for the same error while maintaining continuous instruction execution.
Solution Approach 2:
The system implements a feedback mechanism where the memory controller monitors error locations and compares them against the pre-loading buffer status. This feedback loop enables the system to distinguish between new errors requiring processor attention and recurring errors already being handled, thereby preventing infinite interrupt loops while maintaining reliable error detection.
2Productivity
If interrupts are deactivated to prevent repeated triggering for the same error, then the infinite loop is avoided, but the processor cannot determine the location of the erroneous instruction for correction
Solution Approach 1:
The patent implements a pre-loading mechanism that proactively loads instructions into a buffer before they are executed by the processor. This preliminary action allows the system to track which instructions are currently being processed and suppress interrupts only for those instructions, while maintaining interrupt capability for new errors at different locations. The error location information is preserved through the pre-loading tracking mechanism.
3Reliability
If the memory controller corrects errors directly in the memory by erasing and re-writing information, then the error is permanently fixed, but the operation takes relatively long time especially for non-volatile memory
Solution Approach 1:
The patent applies partial correction by using the error detection capability to identify and suppress interrupts for already-processed erroneous instructions, rather than performing full correction of all errors in memory. This partial action approach corrects the immediate problem of repeated interrupts without requiring time-consuming memory rewrite operations, while still maintaining system reliability.
Data Source
AI summary
The present disclosure provides an integrated circuit comprising a memory controller configured to transmit information stored in a memory to a processing unit. An example memory controller includes an error detection circuit configured to detect an error in the information by implementing an error correcting code algorithm, and to generate an interrupt signal in the event of detection of at least one error in the information and a transmission control circuit configured to transmit the interrupt signal to the processing unit only when the error is detected for the first time in the information by the error detection circuit.